-
1
-
-
33747750894
-
"IDDQ testing because zero defects isn't enough: A Philips perspective,"
-
1991. pp. 301-305.
-
K. Baker and B. Verfielst, "IDDQ testing because zero defects isn't enough: A Philips perspective," Int. Test Conf., 1991. pp. 301-305.
-
Int. Test Conf.
-
-
Baker, K.1
Verfielst, B.2
-
2
-
-
0024169186
-
'Testing oriented analysis of CMOS IC's with opens,"
-
1988, pp. 344-347.
-
W. Maly, P. Nag, and P. Nigh, 'Testing oriented analysis of CMOS IC's with opens," Pmc. IEEE ICCAD, 1988, pp. 344-347.
-
Pmc. IEEE ICCAD
-
-
Maly, W.1
Nag, P.2
Nigh, P.3
-
4
-
-
0022107260
-
"Fault diagnosis of analog circuits,"
-
Aug. 1985, pp. 1279-1325.
-
J. W. Bandlcr and A. E. Salatna, "Fault diagnosis of analog circuits," Pror. IEEE, Aug. 1985, pp. 1279-1325.
-
Pror. IEEE
-
-
Bandlcr, J.W.1
Salatna, A.E.2
-
6
-
-
0018496008
-
"Calculation of parameter values from node voltage measurements."
-
July 1979, pp. 466-4174.
-
T. N. Trick, W. Mayeda, and A. A. Sakala. "Calculation of parameter values from node voltage measurements." IEEE Trans. Circuits Sy;st., July 1979, pp. 466-4174.
-
IEEE Trans. Circuits Sy;st.
-
-
Trick, T.N.1
Mayeda, W.2
Sakala, A.A.3
-
7
-
-
0026910792
-
"Built-in Self Test (BIST) structures for analog diagnosis with current test data,"
-
vol. 41, pp. 535-539, Aug. 1992.
-
C.-L. Wey and S. Rrishnan, "Built-in Self Test (BIST) structures for analog diagnosis with current test data," IEEE Trans. Instrum. Meus., vol. 41, pp. 535-539, Aug. 1992.
-
IEEE Trans. Instrum. Meus.
-
-
Wey, C.-L.1
Rrishnan, S.2
-
8
-
-
0022313916
-
"Electrical characteristics and testing considerations for gate oxide shorts in CMOS IC's,"
-
Philadelphia, PA, Nov. 1985, pp. 443-451.
-
C. F. Hawkins and J. M. Soden. "Electrical characteristics and testing considerations for gate oxide shorts in CMOS IC's," 1985 Int. Test Conf., Philadelphia, PA, Nov. 1985, pp. 443-451.
-
1985 Int. Test Conf.
-
-
Hawkins, C.F.1
Soden, J.M.2
-
9
-
-
33747760366
-
"Reliability and electrical properties of gate oxide shorts in CMOS IC's," 7986
-
Sept. 1986, pp. 300-309.
-
_, "Reliability and electrical properties of gate oxide shorts in CMOS IC's," 7986 Int. Test Conf., Sept. 1986, pp. 300-309.
-
Int. Test Conf.
-
-
-
10
-
-
0023601212
-
"Measurements of quiescent current for CMOS IC's in production testing,"
-
Sept. 1987, pp. 300-309.
-
L. K. Horinig el. at., "Measurements of quiescent current for CMOS IC's in production testing," /9K7 Int. Test Conf., Sept. 1987, pp. 300-309.
-
/9K7 Int. Test Conf.
-
-
Horinig, L.K.1
-
11
-
-
0024864040
-
"Test generation for current testing,"
-
1989, pp. 194-200.
-
P. Nigh and W. Maly, "Test generation for current testing," Euro. Test Conf.. 1989, pp. 194-200.
-
Euro. Test Conf..
-
-
Nigh, P.1
Maly, W.2
-
12
-
-
84918852980
-
"Analog fault diagnosis: A fault clustering approach,"
-
Rotterdam, Holland, Apr. 1993, pp. 108-115.
-
S. S. Somayajula, E. Sânehei-Sinencio, and J. Pineda de Gyve?, "Analog fault diagnosis: A fault clustering approach," Proc. ETC, Rotterdam, Holland, Apr. 1993, pp. 108-115.
-
Proc. ETC
-
-
Somayajula, S.S.1
Sânehei-Sinencio, E.2
De Pineda Gyve, J.3
-
13
-
-
0027810166
-
"A neuial netwoik approach to hierarchical analog fault diagnosis,"
-
San Antonio, TX. Sept. 1993, pp. 699-706.
-
S. S. Somayajula, "A neuial netwoik approach to hierarchical analog fault diagnosis," AUTOTESTCON '93, San Antonio, TX. Sept. 1993, pp. 699-706.
-
AUTOTESTCON '93
-
-
Somayajula, S.S.1
-
16
-
-
0023576590
-
'Testing CMOS IDD on large devices,"
-
Sept. 1987, pp. 310-315.
-
C. Crapuchettes, 'Testing CMOS IDD on large devices," 1987 Int. Test Con}.. Sept. 1987, pp. 310-315.
-
1987 Int. Test Con}..
-
-
Crapuchettes, C.1
-
17
-
-
0026869827
-
"Design and test rules for CMOS circuits to facilitate IDD! testing of bridging faults,"
-
vol. 11, pp. 659-670. May 1992.
-
K.-J. Lcc and M. A. Breuer, "Design and test rules for CMOS circuits to facilitate IDD! testing of bridging faults," IEEE Trans. Computer-Aided Design, vol. 11, pp. 659-670. May 1992.
-
IEEE Trans. Computer-Aided Design
-
-
Lcc, K.-J.1
Breuer, M.A.2
-
18
-
-
0026257619
-
"Current testing and stuck-at fault comparison on a CMOS chip,"
-
pp. 63-89, Nov. 1991.
-
T. Storey, W. Maly, and J. Andrews, "Current testing and stuck-at fault comparison on a CMOS chip," Electron. Eng., pp. 63-89, Nov. 1991.
-
Electron. Eng.
-
-
Storey, T.1
Maly, W.2
Andrews, J.3
-
19
-
-
33747796970
-
"A new approach lo dynamic IDD testing,"
-
Sept. 1987, pp. 148-157.
-
M. Keating and D. Meyer, "A new approach lo dynamic IDD testing," Int. Test ConJ., Sept. 1987, pp. 148-157.
-
Int. Test ConJ.
-
-
Keating, M.1
Meyer, D.2
-
20
-
-
0027544735
-
"Ijj, testing of oscillating bridging faults in CMOS combinational circuits,"
-
pp. 39-44, Feb. 1993.
-
M. Rica, E. Sicard, and A. Rubio. "Ijj, testing of oscillating bridging faults in CMOS combinational circuits," IEE Proc. Part G, Circuits, Devices Syst., pp. 39-44, Feb. 1993.
-
IEE Proc. Part G, Circuits, Devices Syst.
-
-
Rica, M.1
Sicard, E.2
Rubio, A.3
-
21
-
-
33747771722
-
-
Master's degree thesis, Dept. Elect. Eng., Eindhoven Univ. Technol., Feh. 1991.
-
A. T. H. S. T. M. Kolks, "Test generation for current testing," Master's degree thesis, Dept. Elect. Eng., Eindhoven Univ. Technol., Feh. 1991.
-
"Test Generation for Current Testing,"
-
-
Kolks, A.T.1
-
22
-
-
33747771361
-
"Inductive fault analysis of MOS integrated circuits,"
-
pp. 183-192, 1990.
-
J. P. Shen, W. Maly. and F. J. Ferguson, "Inductive fault analysis of MOS integrated circuits," IEEE Design Test, pp. 183-192, 1990.
-
IEEE Design Test
-
-
Shen, J.P.1
Maly, W.2
Ferguson, F.J.3
-
23
-
-
0024167571
-
"Built-in current testing-Feasibility study,"
-
1988. pp. 340-343.
-
W. Maly and P. Nigh, "Built-in current testing-Feasibility study," Proc. IEEE 1CCAD, 1988. pp. 340-343.
-
Proc. IEEE 1CCAD
-
-
Maly, W.1
Nigh, P.2
-
25
-
-
0024133344
-
"Current sensing for built-in testing of CMOS circuits."
-
Jan. 1988, pp. 454-457.
-
D. B. Feltham, P. Nigh, E. R. Carey, and W. Maly, "Current sensing for built-in testing of CMOS circuits." Proc. IEEE Int. Conf. Computer Design, Jan. 1988, pp. 454-457.
-
Proc. IEEE Int. Conf. Computer Design
-
-
Feltham, D.B.1
Nigh, P.2
Carey, E.R.3
Maly, W.4
-
26
-
-
0027148018
-
"A 2-ns detecting time, 2-ram CMOS built-in current sensing circuit
-
vol. 28, pp. 72-77, Jan. 1993.
-
26) T.-E. Shen, J. C. Daly, and J.-C. Eo, "A 2-ns detecting time, 2-ram CMOS built-in current sensing circuit," IEEE J. Solid-State Circuits, vol. 28, pp. 72-77, Jan. 1993.
-
IEEE J. Solid-State Circuits
-
-
Shen, T.-E.1
Daly, J.C.2
Eo, J.-C.3
-
27
-
-
33747797633
-
"Current source adjusts for offset,"
-
76, Feb. 18, 1993.
-
J. Stoughto, "Current source adjusts for offset," Electron. Design, p. 76, Feb. 18, 1993.
-
Electron. Design, P.
-
-
Stoughto, J.1
-
28
-
-
0024282114
-
"Current copier cells,"
-
vol. 24, pp. 1560-1562, Dec. 1988.
-
S. J. Daubert, D. Callancourt, and Y. P. Tsividis, "Current copier cells," Electron. Lett., vol. 24, pp. 1560-1562, Dec. 1988.
-
Electron. Lett.
-
-
Daubert, S.J.1
Callancourt, D.2
Tsividis, Y.P.3
-
29
-
-
0026882274
-
"Measurement of VESI power supply current by electronic-beam prohing,"
-
vol. 27. pp. 948-958, June 1992.
-
K. A. Jenkins and R. E. Franch, "Measurement of VESI power supply current by electronic-beam prohing," IF.F.E J. Solid-Slate Circuits, vol. 27. pp. 948-958, June 1992.
-
IF.F.E J. Solid-Slate Circuits
-
-
Jenkins, K.A.1
Franch, R.E.2
-
31
-
-
0001900396
-
"Test and design testability of analog and mixed-mode integrated circuits: Theoretical aspects and pragmatical approaches,"
-
D. G. Haigh, J. E. Huertas, P. A. Humblet, M. Kunt, Fds. New York: Flsevier, 1993, pp. 75-156.
-
J. E. Huertas, "Test and design testability of analog and mixed-mode integrated circuits: Theoretical aspects and pragmatical approaches," Selected Topics in Circuits and Systems. D. G. Haigh, J. E. Huertas, P. A. Humblet, M. Kunt, Fds. New York: Flsevier, 1993, pp. 75-156.
-
Selected Topics in Circuits and Systems.
-
-
Huertas, J.E.1
-
33
-
-
0029342165
-
"An analytical MOS transistor model valid in all regions of operation and declicted to low voltage and low current applications,"
-
vol. 8, pp. 83-114, 1995.
-
C. C. Eiiz, F. Krummenacuer, and E. A. Villoz, "An analytical MOS transistor model valid in all regions of operation and declicted to low voltage and low current applications," Analog Integral. Circuits Signal Processing, vol. 8, pp. 83-114, 1995.
-
Analog Integral. Circuits Signal Processing
-
-
Eiiz, C.C.1
Krummenacuer, F.2
Villoz, E.A.3
-
34
-
-
0029180063
-
"Estimating key parameters in the KKV MOS T model for analogue design and simulation,"
-
1995, pp. 1588-1991.
-
G. A. S. Machado, C. C. Enz, and M. Bucher, "Estimating key parameters in the KKV MOS T model for analogue design and simulation," Proc. Int. Symp. Circuits Syst., 1995, pp. 1588-1991.
-
Proc. Int. Symp. Circuits Syst.
-
-
Machado, G.A.S.1
Enz, C.C.2
Bucher, M.3
-
35
-
-
0343415457
-
"Can supply current monitor ing be applied to the testing of analogue and digital portions of mixed ASICs?"
-
1991, pp. 538-542.
-
D. Champlin, G. Taylor, and B. Bannister, "Can supply current monitor ing be applied to the testing of analogue and digital portions of mixed ASICs?" Proc. IEEE Test. Conf., 1991, pp. 538-542.
-
Proc. IEEE Test. Conf.
-
-
Champlin, D.1
Taylor, G.2
Bannister, B.3
-
36
-
-
33747806263
-
"Concurrent self-test of switched-current circuits based on the S2I technique,"
-
Jan. 8-9, 1994, pp. 24-30.
-
G. Saether, C. Tonmazou, G. Taylor, K. Eckersall, and I. Bell, "Concurrent self-test of switched-current circuits based on the S2I technique," Proc. Norchip Conf., Jan. 8-9, 1994, pp. 24-30.
-
Proc. Norchip Conf.
-
-
Saether, G.1
Tonmazou, C.2
Taylor, G.3
Eckersall, K.4
Bell, I.5
|