-
1
-
-
40549121772
-
-
Online, Available
-
R. Gocring, "Leakage takes priority at 65 nm," [Online]. Available: http://www.eetimes.com/news/latest/showArticle.jhtml7articleID= 175804055
-
Leakage takes priority at 65 nm
-
-
Gocring, R.1
-
3
-
-
33748554808
-
Ultralowvoltage, minimum-energy CMOS
-
Jul./Sep
-
S. Hanson, B. Zhai, K. Bernstein, D. Blaauw, A. Bryant, L. Chang, K. K. Das, W. Haensch, E. J. Nowak, and D. M. Sylvester, "Ultralowvoltage, minimum-energy CMOS," IBM J. Res. Dev., vol. 50, no. 4/5, pp. 469-489, Jul./Sep. 2006.
-
(2006)
IBM J. Res. Dev
, vol.50
, Issue.4-5
, pp. 469-489
-
-
Hanson, S.1
Zhai, B.2
Bernstein, K.3
Blaauw, D.4
Bryant, A.5
Chang, L.6
Das, K.K.7
Haensch, W.8
Nowak, E.J.9
Sylvester, D.M.10
-
4
-
-
0742304015
-
A Statistical Model for Extracting Geometric Sources of Transistor Performance Variation
-
Jan
-
S. T. Ma, A. Keshavarzi, V. De, and J. R. Brews, "A Statistical Model for Extracting Geometric Sources of Transistor Performance Variation," IEEE Trans. Electron Devices, vol. 51, no. 1, pp. 36-51, Jan. 2004.
-
(2004)
IEEE Trans. Electron Devices
, vol.51
, Issue.1
, pp. 36-51
-
-
Ma, S.T.1
Keshavarzi, A.2
De, V.3
Brews, J.R.4
-
5
-
-
33748535403
-
High-Performance CMOS variability in the 65-nm regime and beyond
-
Jul
-
K. Bernstein, D. J. Frank, A. E. Gattiker, W. Haensch, B. L. Ji, S. R. Nassif, E. J. Nowak, D. J. Pearson, and N. J. Rohrer, "High-Performance CMOS variability in the 65-nm regime and beyond," IBM J. Res. Dev., vol. 50, no. 4/5, pp. 433-449, Jul. 2006.
-
(2006)
IBM J. Res. Dev
, vol.50
, Issue.4-5
, pp. 433-449
-
-
Bernstein, K.1
Frank, D.J.2
Gattiker, A.E.3
Haensch, W.4
Ji, B.L.5
Nassif, S.R.6
Nowak, E.J.7
Pearson, D.J.8
Rohrer, N.J.9
-
6
-
-
0042912833
-
Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs
-
Sep
-
A. Asenov, A. R. Brown, J. H. Davies, S. Kaya, and G. Slavcheva, "Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs," IEEE Trans. Electron Devices, vol. 50, no. 9, pp. 1837-1852, Sep. 2003.
-
(2003)
IEEE Trans. Electron Devices
, vol.50
, Issue.9
, pp. 1837-1852
-
-
Asenov, A.1
Brown, A.R.2
Davies, J.H.3
Kaya, S.4
Slavcheva, G.5
-
8
-
-
85001841209
-
Experimental study of Vt fluctuations using an 8K MOSFET array
-
T. Mizuno, J. Okamura, and A. Toriumi, "Experimental study of Vt fluctuations using an 8K MOSFET array," in Proc. Symp. VLSI Tech., 1993, pp. 41-42.
-
(1993)
Proc. Symp. VLSI Tech
, pp. 41-42
-
-
Mizuno, T.1
Okamura, J.2
Toriumi, A.3
-
9
-
-
0028548950
-
t fluctuations due to statistical variation of channel dopant number in MOSFETs
-
PP, Nov
-
t fluctuations due to statistical variation of channel dopant number in MOSFETs," IEEE Trans. Electron Devices, vol. 41, no. 11, PP. 2216-2221, Nov. 1994.
-
(1994)
IEEE Trans. Electron Devices
, vol.41
, Issue.11
, pp. 2216-2221
-
-
Mizuno, T.1
Okamura, J.2
Toriumi, A.3
-
10
-
-
0026837975
-
t
-
Mar
-
t," IEEE Trans. Electron Devices, vol. 39, no. 3, pp. 634-639, Mar. 1992.
-
(1992)
IEEE Trans. Electron Devices
, vol.39
, Issue.3
, pp. 634-639
-
-
Nishinohara, K.1
Shigyo, N.2
Wada, T.3
-
11
-
-
0027813761
-
Three-dimensional "atomistic" simulation of discrete random dopant distribution effects in sub-0.1 μ m MOSFETs
-
H. S. Wong and Y. Taur, "Three-dimensional "atomistic" simulation of discrete random dopant distribution effects in sub-0.1 μ m MOSFETs," in Int. Electron Devices Meeting Tech. Dig., 1993, pp. 705-708.
-
(1993)
Int. Electron Devices Meeting Tech. Dig
, pp. 705-708
-
-
Wong, H.S.1
Taur, Y.2
-
12
-
-
0035308547
-
The impact of intrinsic device fluctuations on CMOS SRAM cell stability
-
Apr
-
A. Bhavnagarwala, X. Tang, and J. D. Meindl, "The impact of intrinsic device fluctuations on CMOS SRAM cell stability," IEEE J. Solid-State Circuits, vol. 36, no. 4, pp. 658-665, Apr. 2001.
-
(2001)
IEEE J. Solid-State Circuits
, vol.36
, Issue.4
, pp. 658-665
-
-
Bhavnagarwala, A.1
Tang, X.2
Meindl, J.D.3
-
13
-
-
0032320827
-
Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 μ m MOSFET's: A 3-D "atomistic" simulation study
-
Dec
-
A. Asenov, "Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 μ m MOSFET's: A 3-D "atomistic" simulation study," IEEE Trans. Electron Devices, vol. 45, no. 12, pp. 2505-2513, Dec. 1998.
-
(1998)
IEEE Trans. Electron Devices
, vol.45
, Issue.12
, pp. 2505-2513
-
-
Asenov, A.1
-
14
-
-
0142196052
-
Comparison of adaptive body bias (ABB) and adaptive supply voltage (ASV) for improving delay and leakage under the presence of process variation
-
Oct
-
T. Chen and S. Naffziger, "Comparison of adaptive body bias (ABB) and adaptive supply voltage (ASV) for improving delay and leakage under the presence of process variation," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 11, no. 5, pp. 888-899, Oct. 2003.
-
(2003)
IEEE Trans. Very Large Scale Integr. (VLSI) Syst
, vol.11
, Issue.5
, pp. 888-899
-
-
Chen, T.1
Naffziger, S.2
-
15
-
-
28444444598
-
Analysis and mitigation of variability in subthreshold design
-
San Diego, CA, Aug
-
B. Zhai, S. Hanson, D. Blaauw, and D. Sylvester, "Analysis and mitigation of variability in subthreshold design," in Proc. Int. Symp. Low Power Elect. Design (ISLPED), San Diego, CA, Aug. 2005, pp. 20-25.
-
(2005)
Proc. Int. Symp. Low Power Elect. Design (ISLPED)
, pp. 20-25
-
-
Zhai, B.1
Hanson, S.2
Blaauw, D.3
Sylvester, D.4
-
16
-
-
0032097341
-
Radiation effects in advanced microelectronics technologies
-
Jun
-
A. H. Johnston, "Radiation effects in advanced microelectronics technologies," IEEE Trans. Nucl. Sci., vol. 45, no. 3, pp. 1339-1354, Jun. 1998.
-
(1998)
IEEE Trans. Nucl. Sci
, vol.45
, Issue.3
, pp. 1339-1354
-
-
Johnston, A.H.1
-
17
-
-
0032684765
-
Time redundancy based soft-error tolerance to rescue nanometer technologies
-
M. Nicolaidis, "Time redundancy based soft-error tolerance to rescue nanometer technologies," in Proc. VLSI Test Symp., 1999, pp. 86-94.
-
(1999)
Proc. VLSI Test Symp
, pp. 86-94
-
-
Nicolaidis, M.1
-
18
-
-
0036082034
-
Soft error rate mitigation techniques for modern microcircuits
-
D. G. Mavis and P. H. Eaton, "Soft error rate mitigation techniques for modern microcircuits," in Proc 40th Ann. Reliab. Phys. Symp., 2002, pp. 216-225.
-
(2002)
Proc 40th Ann. Reliab. Phys. Symp
, pp. 216-225
-
-
Mavis, D.G.1
Eaton, P.H.2
-
19
-
-
11044223633
-
SET pulse width measurements using a variable temporal latch technique
-
Dec
-
P. Eaton, J. Benedetto, D. Mavis, K. Avery, M. Sibley, M. Gadlage, and T. Turflinger, "SET pulse width measurements using a variable temporal latch technique," IEEE Trans. Nucl. Sci., vol. 51, no. 6, pp. 3285-3290, Dec. 2004.
-
(2004)
IEEE Trans. Nucl. Sci
, vol.51
, Issue.6
, pp. 3285-3290
-
-
Eaton, P.1
Benedetto, J.2
Mavis, D.3
Avery, K.4
Sibley, M.5
Gadlage, M.6
Turflinger, T.7
-
20
-
-
33144460955
-
RHBD techniques for mitigating effects of single-event hits using guard-gates
-
Dec
-
A. Balasubramanian, B. L. Bhuva. J. D. Black, and L. W. Massengill, "RHBD techniques for mitigating effects of single-event hits using guard-gates," IEEE Trans. Nucl. Sci., vol. 52, no. 6, pp. 2531-2535, Dec. 2005.
-
(2005)
IEEE Trans. Nucl. Sci
, vol.52
, Issue.6
, pp. 2531-2535
-
-
Balasubramanian, A.1
Bhuva, B.L.2
Black, J.D.3
Massengill, L.W.4
-
21
-
-
28044464102
-
Analytical semi-empirical model for SER sensitivity estimation of deep-submicron CMOS circuits
-
T. Heijmen, "Analytical semi-empirical model for SER sensitivity estimation of deep-submicron CMOS circuits," in Proc. Int. On-Line Testing Symp., 2005, pp. 3-8.
-
(2005)
Proc. Int. On-Line Testing Symp
, pp. 3-8
-
-
Heijmen, T.1
-
22
-
-
0034450511
-
Impact of CMOS technology scaling on the atmospheric neutron soft error rate
-
Dec
-
P. Hazucha and C. S vensson, "Impact of CMOS technology scaling on the atmospheric neutron soft error rate," IEEE Trans. Nucl. Sci., vol. 47, no. 6, pp. 2586-2594, Dec. 2000.
-
(2000)
IEEE Trans. Nucl. Sci
, vol.47
, Issue.6
, pp. 2586-2594
-
-
Hazucha, P.1
vensson, C.S.2
-
23
-
-
34250777043
-
Radiation-induced soft error rates of advanced CMOS bulk devices
-
N. Seifert, P. Slankard, M. Kirsch, B. Narasimham, V. Zia, C. Brookreson, A. Vo, S. Mitra, B. Gill, and J. Maiz, "Radiation-induced soft error rates of advanced CMOS bulk devices," in Proc. IEEE Int. Reliab. Phys. Symp., 2006, pp. 217-225.
-
(2006)
Proc. IEEE Int. Reliab. Phys. Symp
, pp. 217-225
-
-
Seifert, N.1
Slankard, P.2
Kirsch, M.3
Narasimham, B.4
Zia, V.5
Brookreson, C.6
Vo, A.7
Mitra, S.8
Gill, B.9
Maiz, J.10
-
24
-
-
29444460344
-
Impacts of front-end and middle-end process modifications on terrestrial soft error rate
-
Sep
-
P. Roche and G. Gasiot, "Impacts of front-end and middle-end process modifications on terrestrial soft error rate," IEEE Trans. Dev. Mater. Reliab., vol. 5, no. 3, pp. 382-396, Sep. 2005.
-
(2005)
IEEE Trans. Dev. Mater. Reliab
, vol.5
, Issue.3
, pp. 382-396
-
-
Roche, P.1
Gasiot, G.2
-
25
-
-
34547254841
-
A comprehensive study on the soft-error rate of flip-flops from 90-nm production libraries
-
Mar
-
T. Heijmen, P. Roche, G. Gasiot, K. R. Forbes, and D. Giot, "A comprehensive study on the soft-error rate of flip-flops from 90-nm production libraries," IEEE Trans. Dev. Mater. Reliab., vol. 7, no. 1, pp. 84-96, Mar. 2007.
-
(2007)
IEEE Trans. Dev. Mater. Reliab
, vol.7
, Issue.1
, pp. 84-96
-
-
Heijmen, T.1
Roche, P.2
Gasiot, G.3
Forbes, K.R.4
Giot, D.5
-
26
-
-
33846289912
-
Modeling SEUs in 65 nm SOI semiconductor devices
-
Dec
-
A. KleinOsowski, P. Oldiges, R. Q. Williams, and P. M. Solomon, "Modeling SEUs in 65 nm SOI semiconductor devices," IEEE Trans. Nucl. Sci., vol. 53, no. 6, pp. 3321-3328, Dec. 2006.
-
(2006)
IEEE Trans. Nucl. Sci
, vol.53
, Issue.6
, pp. 3321-3328
-
-
KleinOsowski, A.1
Oldiges, P.2
Williams, R.Q.3
Solomon, P.M.4
-
27
-
-
0029752087
-
Critical charge calculations for a bipolar SRAM array
-
L. B. Freeman, "Critical charge calculations for a bipolar SRAM array," IBM J. R&D, vol. 40, pp. 119-129, 1996.
-
(1996)
IBM J. R&D
, vol.40
, pp. 119-129
-
-
Freeman, L.B.1
-
28
-
-
33847308243
-
Impact of process variation on SE vulnerability of nanometer VLSI circuits
-
Q. Ding, R. Luo, and Y. Xie, "Impact of process variation on SE vulnerability of nanometer VLSI circuits," in Proc. 6th Int. Conf. ASIC, 2005, pp. 24-27.
-
(2005)
Proc. 6th Int. Conf. ASIC
, pp. 24-27
-
-
Ding, Q.1
Luo, R.2
Xie, Y.3
-
29
-
-
28044459391
-
Alpha-particle-induced SER of embedded SRAMS affected by variations in process parameters and by the use of process options
-
Nov
-
T. Heijmen and B. Kruseman, "Alpha-particle-induced SER of embedded SRAMS affected by variations in process parameters and by the use of process options," Solid-State Electron., vol. 49, no. 11, pp. 1783-1790, Nov. 2005.
-
(2005)
Solid-State Electron
, vol.49
, Issue.11
, pp. 1783-1790
-
-
Heijmen, T.1
Kruseman, B.2
-
30
-
-
34250713365
-
A comparative study on the SER of flip-flops from 90-nm production libraries
-
T. Heijmen, P. Roche, G. Gasiot, and K. R. Forbes, "A comparative study on the SER of flip-flops from 90-nm production libraries," in Proc. IEEE Int. Reliab. Phys. Symp., 2006, pp. 204-211.
-
(2006)
Proc. IEEE Int. Reliab. Phys. Symp
, pp. 204-211
-
-
Heijmen, T.1
Roche, P.2
Gasiot, G.3
Forbes, K.R.4
-
31
-
-
45749150092
-
Trends in pulse widths and pulse shapes of a commercial deep submicron CMOS process at 90 nm
-
presented at the, Long Beach, CA
-
S. DasGupta, A. F. Witulski, B. L. Bhuva, M. L. Ailes, L. W. Massengill, O. A. Amusan, J. R. Ahlbin, R. D. Schrimpf, and R. A. Reed, "Trends in pulse widths and pulse shapes of a commercial deep submicron CMOS process at 90 nm," presented at the Single Event Effects (SEE) Symp., Long Beach, CA, 2007.
-
(2007)
Single Event Effects (SEE) Symp
-
-
DasGupta, S.1
Witulski, A.F.2
Bhuva, B.L.3
Ailes, M.L.4
Massengill, L.W.5
Amusan, O.A.6
Ahlbin, J.R.7
Schrimpf, R.D.8
Reed, R.A.9
-
32
-
-
37249021916
-
Design techniques to reduce SET pulse widths in deep-submicron combinational logic
-
Dec, submitted for publication
-
O. A. Amusan, L. W. Massengill, B. L. Bhuva, S. Dasgupta, A. F. Witulski, and J. R. Ahlbin, "Design techniques to reduce SET pulse widths in deep-submicron combinational logic," IEEE Trans. Nucl. Sci., Dec. 2007, submitted for publication.
-
(2007)
IEEE Trans. Nucl. Sci
-
-
Amusan, O.A.1
Massengill, L.W.2
Bhuva, B.L.3
Dasgupta, S.4
Witulski, A.F.5
Ahlbin, J.R.6
-
33
-
-
37249087454
-
Nvidia GeForceFX 5700 ultra graphics processor structural analysis
-
CHIPWORKS, Tech. Rep. SAR-0408-002
-
CHIPWORKS, "Nvidia GeForceFX 5700 ultra graphics processor structural analysis," Tech. Rep. SAR-0408-002, 2005.
-
(2005)
-
-
-
34
-
-
84858511868
-
-
Vanderbilt University, Online, Available
-
Vanderbilt University, Nashville, TN, "ACCRE Computing Cluster," 2007 [Online]. Available: http://www.accre.vanderbilt.edu
-
(2007)
ACCRE Computing Cluster
-
-
Nashville, T.N.1
|