DCache warn: An I-Fetch policy to increase SMT efficiency

Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2004 (Abstracts and CD-ROM)

Volumn 18, Issue , 2004, Pages 1037-1046

  Cazorla, Francisco J ^a   Ramirez, Alex ^a   Valero, Mateo ^a   Fernández, Enrique ^b  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^b UNIVERSITY OF LAS PALMAS DE GRAN CANARIA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; DATA REDUCTION; ELECTRIC POWER UTILIZATION; PUBLIC POLICY; SERVERS;

DATA GATING POLICY (DG); FUNCTIONAL UNITS (FU); SIMULTANEOUS MULTITHREADING (SMT) PROCESSORS; SUPERSCALAR PROCESSORS;

PROGRAM PROCESSORS;

EID: 12444343068     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

1. J. Burns and J.-L. Gaudiot. Exploring the SMT fetch bottleneck. In Proceedings of the 3rd Workshop on Multithreaded Execution, Architecture, and Compilation, 1999.
2. J. Burns and J.-L. Gaudiot. Quantifying the SMT layout overhead- does SMT pull its weight? In Proceedings of the 6th Intl. Conference on High Performance Computer Architecture, pages 109-120, Jan. 2000.
3. A. El-Moursy and D. Albonesi. Front-end policies for improved issue efficiency in SMT processors. In Proceedings of the 9th Intl. Conference on High Performance Computer Architecture, pages 31-42, Feb. 2003.
4. A. Falcon, A. Ramirez, and M. Valero. A low complexity, high-performance fetch unit for simultaneous multithreading processors. Proceedings of the 10th Intl. Conference on High Performance Computer Architecture, Feb. 2004.
5. H. Hirata, K. Kimura, S. Nagamine, Y. Mochizuki, A. Nishimura, Y. Nakase, and T. Nishizawa. An elementary processor architecture with simultaneous instruction issuing from multiple threads. In Proc. of the 19th Annual ISCA, pages 136-145, May 1992.
6. R. Kalla, B. Sinharoy, and J. Tendler. SMT implementation in POWER 5. Hot Chips, 15, Aug. 2003.
7. C. Limousin, J. Sebot, A. Vartanian, and N. Drach-Temam. Improving 3D geometry transformations on a simultaneous multithreaded SIMD processor. In Proc. of the 15th Intl. Conference on Supercomputing, pages 236-245, May 2001.
8. K. Luo, J. Gummaraju, and M. Franklin. Balancing throughput and fairness in SMT processors. In Proceedings of the International Symposium on Performance Analysis of Systems and Software, pages 164-171, Nov. 2001.
9. D. T. Marr, F. Binns, D. Hill, G. Hinton, D. Koufaty, J. A. Miller, and M. Upton. Hyper-threading technology architecture and microarchitecture. Intel Technology Journal, 6(1), Feb. 2002.
10. T. Sherwood, E. Perelman, and B. Calder. Basic block distribution analysis to find periodic behavior and simulation points in applications. In Proceedings of the 10th Intl. Conference on Parallel Architectures and Compilation Techniques, Sept. 2001.
11. D. Tullsen and J. Brown. Handling long-latency loads in a simultaneous multithreaded processor. In Proceedings of the 34th Annual ACM/IEEE Intl. Symposium on Microarchitecture, pages 318-327, Dec. 2001.
12. D. Tullsen, S. Eggers, J. Emer, H. Levy, J. Lo, and R. Stamm. Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor. In Proceedings of the 23th Annual Intl. Symposium on Computer Architecture, pages 191-202, Apr. 1996.
13. D. Tullsen, S. Eggers, and H. M. Levy. Simultaneous multi-threading: Maximizing on-chip parallelism. In Proceedings of the 22th Annual Intl. Symposium on Computer Architecture, pages 392-403, 1995.
14. W. Yamamoto and M. Nemirovsky. Increasing superscalar performance through multistreaming. In Proceedings of the 4th Intl. Conference on Parallel Architectures and Compilation Techniques, pages 49-58, June 1995.