Electromagnetic-thermal characterization of on on-chip coupled (A)symmetrical interconnects

IEEE Transactions on Advanced Packaging

Volumn 30, Issue 4, 2007, Pages 851-863

  Yin, Wen Yan ^a   Kang, Kai ^b,c   Mao, Jun Fa ^a  

^a SHANGHAI JIAO TONG UNIVERSITY   (China)

^b NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^c INSTITUTE OF MICROELECTRONICS   (Singapore)

Author keywords

Average power handling capability (APHC); Conductive and dielectric attenuation constants; Coupled metal insulator silicon interconnects; Distributed parameters; Frequency and temperature dependent; Pulse waveform distortion; Thermal model

Indexed keywords

CHARACTERIZATION; COMPUTER SIMULATION; DIELECTRIC PROPERTIES; ELECTRIC CONDUCTANCE; ELECTRIC CONDUCTIVITY; ELECTRIC IMPEDANCE; INTERCONNECTION NETWORKS; SEMICONDUCTING SILICON; SUBSTRATES; THERMODYNAMIC PROPERTIES;

DIELECTRIC ATTENUATION CONSTANT; DISTRIBUTED PARAMETER; PULSE WAVEFORM DISTORTION; THERMAL MODEL;

ELECTRONICS PACKAGING;

EID: 36348938807     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/TADVP.2007.908016     Document Type: Article

References (35)

1. H. Hasegawa, M. Furukawa, and H. Yanai, "Properties of microstrip line on si-sio2 system," IEEE Trans Microw Theory Tech, vol. MTT-19, no. 11, pp. 869-881, Nov. 1971.
2. K. W. Goossen and R. B. Hammond, "Modeling of picosecond pulse propagation in microstrip interconnects on integrated circuits," IEEE Trans Microw Theory Tech, vol. 37, no. 3, pp. 469-478, Mar. 1989.
3. S. Zaage and E. Groteluschen, "Characterization of the broadband transmission behavior of interconnections on silicon substrates," IEEE Transactions Components, Hybrids, Manuf. Technol., vol. 16, no. 7, pp. 686-691, Nov. 1993.
4. D. F. Williams, "Metal-insulator-semiconductor transmission lines," IEEE Trans Microw Theory Tech, vol. 47, no. 2, pp. 176-181, Feb. 1999.
5. W. Ryu, S. H. Baik, H. Kim, J. Kim, M. Sung, and J. Kim, "Embedded microstrip interconnection lines for gigahertz digital circuits," IEEE Trans. Adv. Packag., vol. 23, no. 3, pp. 495-503, Aug. 2000.
6. Z. F. Jin, J. J. Laurin, and Y. Savaria, "A practical approach to model long MIS interconnects in VLSI circuits," IEEE Trans. Very Large Scale (VLSI) Syst., vol. 10, no. 4, pp. 494-507, Aug. 2002.
7. D. D. Roest, H. Ymeri, S. Vandenberghe, M. Stucchi, D. Schueurs, K. Maex, and B. Nauwelaers, "Some measurement results for frequency-dependent inductance of IC interconnects on a lossy silicon substrate," IEEE Electron Device Lett., vol. 23, no. 2, pp. 103-104, Feb. 2002.
8. B. Kleveland, X. Qi, L. Madden, T. Furusawa, R. W. Dutton, M. A. Horowitz, and S. S. Wong, "High-frequency characterization of on-chip digital interconnects," IEEE J. Solid-State Circuits, vol. 37, no. 6, pp. 716-725, Jun. 2002.
9. J. P. K. Gilb and C. A. Balanis, "MIS slow-wave structure over a wide range of parameters," IEEE Trans Microw Theory Tech, vol. 40, no. 12, pp. 2148-2154, Dec. 1992.
10. V. K. Tripathi and N. Orhanovic, "Time-domain characterization and analysis of dispersive interconnects," IEEE Trans. Circuits Syst. I. Fundam. Theor. Appl., vol. 39, no. 11, pp. 938-945, 1992.
11. S. Voranantakul, J. L. Prince, and P. Hsu, "Crosstalk analysis for high-speed pulse propagation in lossy electrical interconnections," IEEE Trans. Comp., Hybrids, Manufact. Technol., vol. 16, no. 1, pp. 127-136, Feb. 1993.
12. J. A. Davis and J. D. Meindl, "Compact distributed RLC interconnect models-part II: Coupled line transient expressions and peak crosstalk in multilevel networks," IEEE Trans. Electron Devices, vol. 47, no. 11, pp. 2078-2087, Nov. 2000.
13. M. Sung, W. Ryu, H. Kim, J. Kim, and J. Kim, "An efficient crosstalk parameter extraction method for high-speed interconnection lines," IEEE Trans. Adv. Packag., vol. 23, no. 2, pp. 148-155, May 2000.
14. J. Zheng, Y. C. Hahm, V. K. Tripathi, and A. Weisshaar, "CAD-oriented equivalent-circuit modeling of on-chip interconnects on lossy silicon substrate," IEEE Trans Microw Theory Tech, vol. 48, no. 9, pp. 1443-1451, Sep. 2000.
15. A. Weisshaar, H. Lan, and A. Luoh, "Accurate closed-formed expressions for the frequency dependent line parameters of on-chip interconnects on lossy silicon substrate," IEEE Trans. Adv. Packag., vol. 25, no. 2, pp. 288-296, May 2002.
16. A. Weisshaar and A. Luoh, "Closed-form expressions for the series impedance parameters of on-chip interconnects on multilayer silicon substrates," IEEE Trans. Adv. Packaging, vol. 25, no. 1, pp. 126-134, 2002.
17. C. N. Chiu, "Closed-form expressions for the line-coupling parameters of coupled on-chip interconnects on lossy silicon substrate," Micro. Opt. Tech. Lett., vol. 43, no. 6, pp. 495-498, 2004.
18. T. Y. Chiang, B. Shieh, and K. C. Saraswat, "Impact of joule heating on scaling of deep sub-micron cu/low-k interconnects," in 2002 Symp. VLSI Technol. Dig. Tech. Papers, Honolulu, HI, USA, Jun. 11-13, 2002, pp. 38-39.
19. T. Y. Chiang, K. Banerjee, and K. C. Saraswat, "Analytical thermal model for multilevel VLSI interconnects incorporating via effect," IEEE Electron Device Lett., vol. 23, no. 1, pp. 31-33, Jan. 2002.
20. K. Banerjee and A. Mehrotra, "Global (interconnect) warming," IEEE Circuits Devices Mag, vol. 17, no. 5, pp. 16-32, Sep. 2001.
21. L. Xue, C. C. Liu, H. S. Kim, S. Kim, and S. Tiwari, "Three-dimensional integration: Technology, use, and issues for mixed-signal applications," IEEE Trans. Electron Devices, vol. 50, no. 3, pp. 601-609, Mar. 2003.
22. M. Golio, The RF and Microwave Handbook. Boca Raton, FL: CRC Press, 2001, A-8.
23. N. Arora, Ed., MOSFET Models For VLSI Circuit Simulation Theory and Practice. New York: Springer-Verlag, 1993, pp. 17-33.
24. V. K. Tripathi, "Asymmetric coupled transmission lines in an inhomogeneous medium," IEEE Trans Microw Theory Tech, vol. MTT-23, no. 9, pp. 734-739, Sep. 1975.
25. V. K. Tripathi, "Equivalent circuits and characteristics of inhomogeneous nonsymmetrical coupled-lines two-port circuits," IEEE Trans. Microwave Theor. Tech., vol. MTT-25, no. 2, pp. 140-142, Feb. 1977.
26. G. Wang, X. Qi, Z. Yu, and R. W. Dutton, "Device level modeling of metal-insulator-semiconductor interconnects,," IEEE Trans. Electron Devices, vol. 48, no. 8, pp. 1672-1682, 2001.
27. F. Stellari and A. L. Lacaita, "New formulas of interconnect capacitances based on results of conformal mapping method," IEEE Trans. Electron Devices, vol. 47, no. 1, pp. 222-231, Jan. 2000.
28. Y. J. Yoon and B. Kim, "A new formula for effective dielectric constant in multi-dielectric layer microstrip structure," in Proc. IEEE 9th Topical Meeting Elect. Performance Electron. Packag. (EPEP'00), Oct. 23-25, 2000, pp. 163-167.
29. H. T. Vo, C. Davidson, and F. G. Shi, "New effective dielectric constant model for ultra-high speed microstrip lines on multilayer dielectric substrates, effects of conductor-dielectric inter-phase," in Proc. 52nd Electron. Components Technol. Conf., San Diego, CA, May 28-31, 2002, pp. 86-89.
30. M. Kirschning and R. H. Jansen, "Accurate wide-range design equations for the frequency-dependent characteristic of parallel coupled microstrip lines," IEEE Trans Microw Theory Tech, vol. MTT-32, no. 1, pp. 83-90, Jan. 1984.
31. K. C. Gupta, R. Grag, I. J. Bahl, and P. Bhartia, Microstrip Lines and Slotlines., Artech House Publ., 1996.
32. P. Pramanick and R. R. Mansour, "Dispersion characteristics of square pulse with finite rise time in single, tapered, and coupled microstrip lines," IEEE Trans Microw Theory Tech, vol. 39, no. 12, pp. 2117-2122, Dec. 1991.
33. I. J. Bahl, "Average power handling capability of multilayer microstrip lines," Int. J. RF Microwave Computer-Aided Eng., vol. 11, no. 6, pp. 385-395, Nov. 2001.
34. W. Y. Yin and X. T. Dong, "Wideband characterization of average power handling capabilities of some microstrip interconnects on polyimide and polyimide/gaas substrates," IEEE Trans. Adv. Packag., vol. 28, no. 2, pp. 328-336, May 2005.
35. W. Y. Yin and X. T. Dong, "Wideband average power handling capability of coupled microstrips on polyimide and polyimide/gaas substrates," IEE Proc. Microw. Antennas Propagat., vol. 151, no. 5, pp. 385-392, Oct. 2004.