Three-dimensional integration: Technology, use, and issues for mixed-signal applications

IEEE Transactions on Electron Devices

Volumn 50, Issue 3, 2003, Pages 601-609

  Xue, Lei ^a,b   Liu, Christianto C ^a,b   Kim, Hong Seung ^a,b   Kim, Sang Kevin ^a,b   Tiwari, Sandip ^a,b  

^a IEEE   (United States)

^b Cornell University   (United States)

Author keywords

CMOS integrated circuits; Crosstalk; Mixed signal integrated circuits; Noise coupling; Self heating; Silicon on insulator (SOI) technology; System on chip integration; Three dimensional integration

Indexed keywords

CHEMICAL MECHANICAL POLISHING; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC PROPERTIES; INTERFACES (MATERIALS); LOW TEMPERATURE OPERATIONS; MOS CAPACITORS; MULTILAYERS; SEMICONDUCTOR DEVICE STRUCTURES; SILICON WAFERS; SINGLE CRYSTALS; THERMAL EFFECTS;

DUAL DAMASCENE PROCESS; MULTILAYERS WITH BURIED STRUCTURE; SINGLE-CRYSTAL SILICON; SYSTEM-ON-A-CHIP INTEGRATION; THREE DIMENSIONAL INTEGRATION;

INTEGRATED CIRCUIT LAYOUT;

EID: 0038236501     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2003.810465     Document Type: Article

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