A practical approach to model long MIS interconnects in VLSI circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 10, Issue 4, 2002, Pages 494-507

  Jin, Zhong Fang ^a   Laurin, Jean Jacques ^a   Savaria, Yvon ^a  

^a ÉCOLE POLYTECHNIQUE DE MONTRÉAL   (Canada)

Author keywords

Dielectric losses; Frequency domain; Interconnect modeling; Metal insulator semiconductor (MIS); Microstrip; Skin effect; Time domain; Very large scale integrated (VLSI) circuits

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; DIELECTRIC LOSSES; ELECTRIC RESISTANCE; EQUIVALENT CIRCUITS; FREQUENCY DOMAIN ANALYSIS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; SKIN EFFECT; TIME DOMAIN ANALYSIS;

ELECTROMAGNETIC FIELD ANALYSIS; METAL INSULATOR SEMICONDUCTOR INTERCONNECTS;

VLSI CIRCUITS;

EID: 0036705179     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2002.800520     Document Type: Article

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