Towards a new nanoelectronic cosmology

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 33-39

  Hartmann, Joël ^a  

^a STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; COSMOLOGY; LOGIC DESIGN; LOGIC PROGRAMMING; PARAMETER ESTIMATION;

GLOBAL PERFORMANCES; NANOELECTRONIC COSMOLOGY; NANOMETER DIMENSIONS; SYSTEM ASPECTS;

NANOELECTRONICS;

EID: 34548858419     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2007.373575     Document Type: Conference Paper

References (35)

1. S.-F. Huang, C. Wann, Y.-S. Huang et al., "Scalability and Biasing Strategy for CMOS with Active Well Bias," Symp. VLSI Tech., pp. 107-108, June 2001.
2. S. Borkar, "Circuit Techniques for Subthreshold Leakage Avoidance,Control, and Tolerance" IEDM Tech. Dig., pp. 421-424, December 2004.
3. M. Jurczak, M. Skotnicki, T. Paoli et al., "Silicon-On-Nothing (SON), an Innovative Process for Advanced CMOS, SON", IEEE TED, Vol. 47, No 11, pp 2179-2187, 2000
4. S. Monfray, T. Skotnicki, Y Morand et al., "50nm Gate-All-Around (GAA) - Silicon On Nothing (SON) - Devices : A simple way to co-integration of GAA transistors within bulk process", Symp. VLSI Tech. Dig., pp 108-109, June 2002
5. Y. Choi, N. Lindert, P. Xuan et al., "Sub-20nm CMOS FinFET Technologies", IEDM Tech. Dig., pp. 421-424, December 2001
6. F. Yang, H.-Y Chen, F.-C. Chen et al., "25nm CMOS Omega FETs", IEDM Tech. Dig., pp. 255-262, December 2002
7. R. Chau, "Advanced Fully-Depleted SOI CMOS Transistors", Proc. SSDM, pp 68-69, 2002
8. J.M. Hergenrother, J.M. Monroe, D. Klemens et al., "The vertical replacement gate (VRG) MOSFET : A 50-nm vertical MOSFET with lithography-independent gate length", IEDM Tech. Dig., pp. 75-78, December 1999
9. D. Hisamoto, D. Kaga, T. Kawamoto et al., "A fully Depleted LeanChannel Transistor (DELTA) - A Novel vertical ultra thin SOI MOSFET", IEDM, Tech. Dig., pp 833-836, December 1989
10. H. Takato, "High performance CMOS Surrounding Gate (SGT) for Ultra High Density LSI's", IEDM Tech. Dig,. pp. 222-225, December 1988
11. Tze-Chiang (T.C.) Chen, "Where CMOS is Going: Trendy Hype vs. Real Technology", ISSCC Tech. Digest, Papers, pp.22, February 2006
12. S. Verdonckt-Vanderbroek, S. Crabbe, E.F. Meyerson et al., "SiGe Channel Heterojunction p-MOSFET's", IEEE Trans. Elec. Dev, Vol.41, No 8, pp. 90-101, 1994
13. V. Kesan, S. Subbana, P. Restle, et al, "High performance 0.25μm p-MOSFETs with Silicon Germanium Channels for 300 K and 77 K Operation", IEDM- Tech. Dig., pp. 25-28, December 1991
14. P. Bouillon, T. Skotnicki, C. Kelaidis et al.,"Search for the Optimal Channel Architecture for 0.18/0.12 μm Bulk CMOS Experimental Study", IEDM, Tech. Dig., pp. 559-562, December 1996
15. 0.3 Channel Heterostructures for 0.15/0.18μm CMOS Process", Proc. ESS-DERC, pp. 144-147, September 1998
16. J. Alieu, T. Skotnicki, E. Josse et al.,"Multiple SiGe Well: A New Channel Architecture for Improving Both NMOS and PMOS Performances", Symp. VLSI Tech., pp. 130-131, June 2000
17. H. Shang, H. Okorn-Schmidt, K. Chan et al., "High Mobility P-Channel Germanium MOSFETs with a Thin Ge Oxynitride Gate Dielectric", IEDM, Tech. Dig.; pp 441-444, December 2002
18. K. Rim, J. L. Hoyt, and J. F. Gibbons, "Transconductance Enhancement in Deep Submicron Strained Si n-MOSFETs", IEDM, Tech. Dig, pp. 707-710, December 1998
19. M.Jurczak, M. Skotnicki, T. Ricci et al., "Study on Enhanced Performance in NMOSFETs on Strained Silicon", Proc. ESSDERC, pp. 304-307, September 1999
20. K. Rim, S. Koester, M. Hargrove et al., "Strained Si NMOSFETs for High Performance CMOS Technology", Symp. VLSI Tech., pp. 59-60. June 2001
21. T. Mizuno,S. Takagi, N. Sugiyama et al., "Electron and hole mobility enhancement in strained-Si MOSFET's on SiGe-on-insulator substrates fabricated by SIMOX technology", IEEE El. Dev. Lett., Vol. 21, No 5, pp 230-232.
22. A. Shimizu, K. Hachimine,N. Ohki et al., "Local Mechanical-Stress Control (LMC): A New Technique for CMOS-Performance Enhancement," IEDM Tech. Dig., pp. 433-436, December 2001.
23. H. Yang, R. Malik, S. Narasimha et al., "Dual Stress Liner for High Performance Sub-45nm Gate Length SOI CMOS Manufacturing," IEDM Tech. Dig., pp. 1075-1078, December 2004.
24. D. Singh, J. Sleight, J. M. Hergenrother et al, "Stress Memorization in High-Performance FDSOIDevices with Ultra-Thin Silicon Channels and 25nm Gate Lengths", IEDM Tech. Dig., December 2005.
25. M. Yang, M. Ieong, L. Shi et al., "High Performance CMOS Fabricated on Hybrid Substrate with Different Crystal Orientations," IEDM Tech Dig., pp. 453-456, December 2003.
26. A. Oishi, O.Fujii, T.Yokoyama et al., "High Performance CMOSFET Technology for 45nm Generation and Scalability of Stress-Induced Mobility Enhancement Technique", IEDM Tech Dig., pp. 239-242, December 2005.
27. B. Nikolic, "Capturing Variability", DAC Tutorial 2, July 24, 2006.
28. F. Boeuf, F. Arnaud, B. Tavel et al., "A conventional 45nm CMOS node low-cost platform for general purpose and low power applications," IEDM Tech. Dig., pp. 425-428, December 2004.
29. M. Lavin, J. Hibbeler, L. Liebmann et al., "Integrating DfM Components into a Cohesive Design-to-Silicon Solution," Design and Process Integration for Microelectronic Manufacturing III, Proc. SPIE, Vol. 5756, pp. 1-12, 2005.
30. S. R. Nassif, "Model to Hardware Matching for nm Scale Technologies", Proc.SISPAD-2006, Plenary Session.
31. MASTAR (Model for Assessment of CMOS Technologies And Roadmaps) is available (free of charge-STMicroelectronics courtesy), upon request to thomas.skotnicki@st.com or frederic.boeuf@st.com
32. P. Lloyd, C. McAndrew, M. McLennan et. al. "Technology CAD at AT&T", Microelectronics J., Vol. 26, No. 2, pp. 79-97, 1995.
33. C. Poirier, R. McGowen, C. Bostak et al., "Power and Temperature Control on a 90nm Itanium-Family Processor," ISSCC Tech. Digest, pp. 304-305, February 2005.
34. F.Boeuf, M. Sellier, B. Duriez et al. "Using MASTAR as a Pre-SPICE Model Generator for Early Technology Assessment and Circuit Simulation", Proc. SSDM, pp 1046-1047, 2006
35. J-P Heliot, J. Hartmann, "Process-Design challenges for CMOS 45nm technology node and beyond", International Conference on IC Design and Technology, May 25, 2006.