Optimisation of Si0.7Ge0.3 channel heterostructures for 0.15/0.18 μm CMOS process

European Solid-State Device Research Conference

Volumn , Issue , 1998, Pages 144-147

  Alieu, J ^a   Bouillon, P ^a   Gwoziecki, R ^a   Moi, D ^a   Bremond, G ^a,b   Skotnicki, T ^a  

^a ORANGE LABS   (France)

^b INSTITUT DES NANOTECHNOLOGIES DE LYON   (France)

Author keywords

[No Author keywords available]

Indexed keywords

BUDGET CONTROL; CMOS INTEGRATED CIRCUITS; GERMANIUM; SILICON ALLOYS;

CHANNEL HETEROSTRUCTURES; CMOS PROCESSS; CMOS TECHNOLOGY; DEVICE ARCHITECTURES; OPTIMAL PROCESS; PMOS TRANSISTORS; SIGE CHANNELS; THERMAL BUDGET;

HETEROJUNCTIONS;

EID: 84908174812     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

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2. D.V. Lang et aI, "Measurement of the band gap of G", Si,.X strained layer heterostructure", Appl. Phy. Let., 45, 1985, p.1333-1335.
3. R. People et aI, "Modulation doping in Ge'. xSjJSi strained layer heterostructures", Appl. Phy. Let., 45 (11),1984, p. 1231-1233.
4. A. Sadek et aI, "Design of Si/SiGe heterojunction complementary metal-oxide-semiconductor transistors", IEEE Tran. Elec. Dev., 43 (8), 1996, p. 1224-1231 .
5. K. Iniewski et aI, "Analytical modeling of the threshold voltages in p-channel Si/SiGelSi MOS structures", Solid State Elec., 36 (5), 1993, p. 775-783.
6. C.G. Sodini etaI, "Charge accumulation and mobility in thin dielectric MOS transistors", Sol. St. E1ee., 25 (9), 1982, p. 833-841