Stress memorization in high-performance FDSOI devices with ultra-thin silicon channels and 25nm gate lengths

Technical Digest - International Electron Devices Meeting, IEDM

Volumn 2005, Issue , 2005, Pages 505-508

  Singh, D V ^a   Sleight, J W ^b   Hergenrother, J M ^a   Ren, Z ^b   Jenkins, K A ^a   Dokumaci, O ^b   Black, L ^c   Chang, J B ^a   Nakayama, H ^d   Chidambarrao, D ^b   Venigalla, R ^b   Pan, J ^c   Natzle, W ^a   Tessier, B L ^b   Nomura, A ^c   Ott, J A ^a   Ieong, M ^b   Haensch, W ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM RESEARCH   (United States)

^c ADVANCED MICRO DEVICES   (United States)

^d SONY CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DRIVE CURRENT; DUAL STRESS LINER (DSL); MOBILITY ENHANCEMENT; STRESS MEMORIZATION (SM); ULTRA-THIN CHANNEL DEVICES;

SILICON ON INSULATOR TECHNOLOGY; STRESS ANALYSIS;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 33847767088     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. H. S. Yang et al., IEDM Tech Dig., 1075 (2004).
2. C. H. Chen et al., Symp. VLSI Tech., Dig. Tech Papers, 56 (2004)
3. D. V. Singh et al., accepted at 2005 IEEE Intl. SOI conference.
4. K. Ota et al., IEDM Tech. Dig., 27 (2002).