-
1
-
-
32844457663
-
The Effect of Technology Scaling on Microarchitecture Structures
-
Technical Report TR-00-02, Dept. of Computer Sciences, Univ. of Texas at Austin, May
-
V. Agarwal, S.W. Keckler, and D. Burger, "The Effect of Technology Scaling on Microarchitecture Structures," Technical Report TR-00-02, Dept. of Computer Sciences, Univ. of Texas at Austin, May 2001.
-
(2001)
-
-
Agarwal, V.1
Keckler, S.W.2
Burger, D.3
-
2
-
-
0029308368
-
Effective Hardware-Based Data Prefetching for High-Performance Processors
-
J.-L. Baer and T.-F. Chen, "Effective Hardware-Based Data Prefetching for High-Performance Processors," IEEE Trans. Computer, vol. 44, no. 5, pp. 609-623, 1995.
-
(1995)
IEEE Trans. Computer
, vol.44
, Issue.5
, pp. 609-623
-
-
Baer, J.-L.1
Chen, T.-F.2
-
3
-
-
0033722744
-
Piranha: A Scalable Architecture Based on Single-Chip Multiprocessing
-
June
-
L.A. Barroso, K. Gharachorloo, R. McNamara, A. Nowatzyk, S. Qadeer, B. Sano, S. Smith, R. Stets, and B. Verghese, "Piranha: A Scalable Architecture Based on Single-Chip Multiprocessing," Proc. 27th Ann. Int'l Symp. Computer Architecture (ISCA '00), pp. 282-293, June 2000.
-
(2000)
Proc. 27th Ann. Int'l Symp. Computer Architecture (ISCA '00)
, pp. 282-293
-
-
Barroso, L.A.1
Gharachorloo, K.2
McNamara, R.3
Nowatzyk, A.4
Qadeer, S.5
Sano, B.6
Smith, S.7
Stets, R.8
Verghese, B.9
-
6
-
-
84944411840
-
Distance Associativity for High-Performance Energy-Efficient Non-Uniform Cache Architectures
-
Dec
-
Z. Chishti, M. Powell, and T.N. Vijaykumar, "Distance Associativity for High-Performance Energy-Efficient Non-Uniform Cache Architectures," Proc. 36th Ann. Int'l Symp. Microarchitecture (MICRO-36), pp. 55-66, Dec. 2003.
-
(2003)
Proc. 36th Ann. Int'l Symp. Microarchitecture (MICRO-36)
, pp. 55-66
-
-
Chishti, Z.1
Powell, M.2
Vijaykumar, T.N.3
-
7
-
-
27544432313
-
Optimizing Replication, Communication, and Capacity Allocation in CMPs
-
June
-
Z. Chishti, M.D. Powell, and T.N. Vijaykumar, "Optimizing Replication, Communication, and Capacity Allocation in CMPs," Proc. 32nd Ann. Int'l Symp. Computer Architecture (ISCA '05), June 2005.
-
(2005)
Proc. 32nd Ann. Int'l Symp. Computer Architecture (ISCA '05)
-
-
Chishti, Z.1
Powell, M.D.2
Vijaykumar, T.N.3
-
8
-
-
36348975404
-
Implementation and Evaluation of On-Chip Network Architectures
-
P. Gratz, C. Kim, R. McDonald, S.W. Keckler, and D. Burger, "Implementation and Evaluation of On-Chip Network Architectures," Proc. 24th IEEE Int'l Conf. Computer Design (ICCD '06), 2006.
-
(2006)
Proc. 24th IEEE Int'l Conf. Computer Design (ICCD '06)
-
-
Gratz, P.1
Kim, C.2
McDonald, R.3
Keckler, S.W.4
Burger, D.5
-
9
-
-
0033880036
-
The Stanford Hydra CMP
-
Dec
-
L. Hammond, B.A. Hubbert, M. Siu, M.K. Prabhu, M. Chen, and K. Olukotun, "The Stanford Hydra CMP," IEEE Micro, pp. 71-84, Dec. 2000.
-
(2000)
IEEE Micro
, pp. 71-84
-
-
Hammond, L.1
Hubbert, B.A.2
Siu, M.3
Prabhu, M.K.4
Chen, M.5
Olukotun, K.6
-
10
-
-
34548239451
-
Hardware Techniques to Reduce Communication Costs in Multiprocessors,
-
PhD dissertation
-
J. Huh, "Hardware Techniques to Reduce Communication Costs in Multiprocessors," PhD dissertation, 2006.
-
(2006)
-
-
Huh, J.1
-
11
-
-
32844471317
-
A NUCA Substrate for Flexible CMP Cache Sharing
-
June
-
J. Huh, C. Kim, H. Shafi, L. Zhang, D. Burger, and S.W. Keckler, "A NUCA Substrate for Flexible CMP Cache Sharing," Proc. 19th ACM Int'l Conf. Supercomputing (ICS '05), pp. 31-40, June 2005.
-
(2005)
Proc. 19th ACM Int'l Conf. Supercomputing (ICS '05)
, pp. 31-40
-
-
Huh, J.1
Kim, C.2
Shafi, H.3
Zhang, L.4
Burger, D.5
Keckler, S.W.6
-
12
-
-
8344246922
-
CQoS: A Framework for Enabling QoS in Shared Caches of CMP Platforms
-
R. Iyer, "CQoS: A Framework for Enabling QoS in Shared Caches of CMP Platforms," Proc. 18th Ann. Int'l Conf. Supercomputing (ICS '04 , pp. 257-266, 2004.
-
(2004)
Proc. 18th Ann. Int'l Conf. Supercomputing (ICS '04
, pp. 257-266
-
-
Iyer, R.1
-
13
-
-
0025429331
-
Improving Direct-Mapped Cache Performance by the Addition of a Small Fully Associative Cache and Prefetch Buffers
-
June
-
N.P. Jouppi, "Improving Direct-Mapped Cache Performance by the Addition of a Small Fully Associative Cache and Prefetch Buffers," Proc. 17th Ann. Int'l Symp. Computer Architecture (ISCA '90), pp. 364-373, June 1990.
-
(1990)
Proc. 17th Ann. Int'l Symp. Computer Architecture (ISCA '90)
, pp. 364-373
-
-
Jouppi, N.P.1
-
14
-
-
3042669130
-
IBM Power5 Chip: A Dual-Core Multithreaded Processor
-
Mar./Apr
-
R. Kalla, B. Sinharoy, and J.M. Tendler, "IBM Power5 Chip: A Dual-Core Multithreaded Processor," IEEE Micro, vol. 24, no. 2, Mar./Apr. 2004.
-
(2004)
IEEE Micro
, vol.24
, Issue.2
-
-
Kalla, R.1
Sinharoy, B.2
Tendler, J.M.3
-
15
-
-
0024668838
-
Inexpensive Implementations of Set-Associativity
-
May
-
R. Kessler, R. Jooss, A. Lebeck, and M. Hill, "Inexpensive Implementations of Set-Associativity," Proc. 16th Ann. Int'l Symp. Computer Architecture (ISCA '89), pp. 131-139, May 1989.
-
(1989)
Proc. 16th Ann. Int'l Symp. Computer Architecture (ISCA '89)
, pp. 131-139
-
-
Kessler, R.1
Jooss, R.2
Lebeck, A.3
Hill, M.4
-
16
-
-
0036949388
-
An Adaptive, Non-Uniform Cache Structure for Wire-Delay Dominated On-Chip Caches
-
Oct
-
C. Kim, D. Burger, and S.W. Keckler, "An Adaptive, Non-Uniform Cache Structure for Wire-Delay Dominated On-Chip Caches," Proc. 10th Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS '02), pp. 211-222, Oct. 2002.
-
(2002)
Proc. 10th Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS '02)
, pp. 211-222
-
-
Kim, C.1
Burger, D.2
Keckler, S.W.3
-
19
-
-
0029666647
-
Evaluation of Design Alternatives for a Multiprocessor Microprocessor
-
May
-
B.A. Nayfeh, L. Hammond, and K. Olukotun, "Evaluation of Design Alternatives for a Multiprocessor Microprocessor," Proc. 23rd Ann. Int'l Symp. Computer Architecture (ISCA '96), pp. 67-77, May 1996.
-
(1996)
Proc. 23rd Ann. Int'l Symp. Computer Architecture (ISCA '96)
, pp. 67-77
-
-
Nayfeh, B.A.1
Hammond, L.2
Olukotun, K.3
-
20
-
-
0029721369
-
The Impact of Shared-Cache Clustering in Small-Scale Shared-Memory Multiprocessors
-
B.A. Nayfeh, K. Olukotun, and J.P. Singh, "The Impact of Shared-Cache Clustering in Small-Scale Shared-Memory Multiprocessors," Proc. Second IEEE Symp. High-Performance Computer Architecture (HPCA '04), p. 74, 1996.
-
(1996)
Proc. Second IEEE Symp. High-Performance Computer Architecture (HPCA '04)
, pp. 74
-
-
Nayfeh, B.A.1
Olukotun, K.2
Singh, J.P.3
-
21
-
-
36849066437
-
Distributed Microarchitectural Protocols in the TRIPS Prototype Processor
-
Dec
-
K. Sankaralingam, R. Nagarajan, R. McDonald, R. Desikan, S. Drolia, M.S.S. Govindan, P. Gratz, D. Gulati, H. Hanson, C. Kim, H. Liu, N. Ranganathan, S. Sethmadhavan, S. Sharif, P. Shivakumar, S.W. Keckler, and D. Burger, "Distributed Microarchitectural Protocols in the TRIPS Prototype Processor," Proc. 39th Int'l Symp. Microarchitecture (MICRO-39), Dec. 2006.
-
(2006)
Proc. 39th Int'l Symp. Microarchitecture (MICRO-39)
-
-
Sankaralingam, K.1
Nagarajan, R.2
McDonald, R.3
Desikan, R.4
Drolia, S.5
Govindan, M.S.S.6
Gratz, P.7
Gulati, D.8
Hanson, H.9
Kim, C.10
Liu, H.11
Ranganathan, N.12
Sethmadhavan, S.13
Sharif, S.14
Shivakumar, P.15
Keckler, S.W.16
Burger, D.17
-
23
-
-
27544498313
-
Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors
-
June
-
E. Speight, H. Shafi, L. Zhang, and R. Rajamony, "Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors," Proc. 32nd Ann. Int'l Symp. Computer Architecture (ISCA '05), June 2005.
-
(2005)
Proc. 32nd Ann. Int'l Symp. Computer Architecture (ISCA '05)
-
-
Speight, E.1
Shafi, H.2
Zhang, L.3
Rajamony, R.4
-
25
-
-
1642371317
-
Dynamic Partitioning of Shared Cache Memory
-
G.E. Suh, L. Rudolph, and S. Devadas, "Dynamic Partitioning of Shared Cache Memory," J. Supercomputing, vol. 28, no. 1, pp. 7-26, 2004.
-
(2004)
J. Supercomputing
, vol.28
, Issue.1
, pp. 7-26
-
-
Suh, G.E.1
Rudolph, L.2
Devadas, S.3
-
26
-
-
34547664408
-
CACTI 4.0
-
Technical Report HPL-2006-86, Hewlett-Packard Laboratories
-
D. Tarjan, S. Thoziyoor, and N. Jouppi, "CACTI 4.0," Technical Report HPL-2006-86, Hewlett-Packard Laboratories, 2006.
-
(2006)
-
-
Tarjan, D.1
Thoziyoor, S.2
Jouppi, N.3
-
27
-
-
0036298603
-
Power4 System Microarchitecture
-
J.M. Tendler, S. Dodson, S. Fields, H. Le, and B. Sinharoy, "Power4 System Microarchitecture," IBM J. Research and Development, vol. 46, no. 1, 2002.
-
(2002)
IBM J. Research and Development
, vol.46
, Issue.1
-
-
Tendler, J.M.1
Dodson, S.2
Fields, S.3
Le, H.4
Sinharoy, B.5
-
28
-
-
0029179077
-
The SPLASH-2 Programs: Characterization and Methodological Considerations
-
June
-
S.C. Woo, M. Ohara, E. Torrie, J.P. Singh, and A. Gupta, "The SPLASH-2 Programs: Characterization and Methodological Considerations," Proc. 22nd Ann. Int'l Symp. Computer Architecture (ISCA '95), pp. 24-36, June 1995.
-
(1995)
Proc. 22nd Ann. Int'l Symp. Computer Architecture (ISCA '95)
, pp. 24-36
-
-
Woo, S.C.1
Ohara, M.2
Torrie, E.3
Singh, J.P.4
Gupta, A.5
-
29
-
-
27544495466
-
Victim Replication: Maximizing Capacity While Hiding Wire Delay in Tiled Chip Multiprocessors
-
June
-
M. Zhang and K. Asanovic, "Victim Replication: Maximizing Capacity While Hiding Wire Delay in Tiled Chip Multiprocessors," Proc. 32nd Ann. Int'l Symp. Computer Architecture (ISCA '05), pp. 336-345, June 2005.
-
(2005)
Proc. 32nd Ann. Int'l Symp. Computer Architecture (ISCA '05)
, pp. 336-345
-
-
Zhang, M.1
Asanovic, K.2
|