An L2-miss-driven early register deallocation for SMT processors

Proceedings of the International Conference on Supercomputing

Volumn , Issue , 2007, Pages 138-147

  Sharkey, Joseph ^a   Ponomarev, Dmitry ^a  

^a State University of New York at Binghamton

Author keywords

Register files; Simultaneous multithreading

Indexed keywords

CACHE MEMORY; COMPUTER SIMULATION; MULTIPROGRAMMING; OPTIMIZATION; PROGRAM PROCESSORS;

CHECKPOINTS; REGISTER ALLOCATION; REGISTER FILES;

FILE ORGANIZATION;

EID: 34548094012     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1274971.1274992     Document Type: Conference Paper

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