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Volumn , Issue , 2005, Pages 7-18

How to fake 1000 registers

Author keywords

[No Author keywords available]

Indexed keywords

LOGICAL REGISTER SPACE; MULTITHREADING; VIRTUAL CONTEXT ARCHITECTURE (VCA);

EID: 33749410234     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2005.21     Document Type: Conference Paper
Times cited : (31)

References (30)
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    • 84944392430 scopus 로고    scopus 로고
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    • Dec.
    • H. Akkary, R. Rajwar, and S. T. Srinivasan. Checkpoint processing and recovery: Towards scalable large instruction window processors. In 36th Ann. Int'l Symp. on Microarchitecture, pages 423-434, Dec. 2003.
    • (2003) 36th Ann. Int'l Symp. on Microarchitecture , pp. 423-434
    • Akkary, H.1    Rajwar, R.2    Srinivasan, S.T.3
  • 8
    • 84859676711 scopus 로고    scopus 로고
    • Free Software Foundation. GNU Compiler Collection. http://gcc.gnu.org.
  • 9
    • 0002327718 scopus 로고    scopus 로고
    • Digital 21264 sets new standard
    • Oct. 28
    • L. Gwennap. Digital 21264 sets new standard. Microprocessor Report, 10(14):11-16, Oct. 28, 1996.
    • (1996) Microprocessor Report , vol.10 , Issue.14 , pp. 11-16
    • Gwennap, L.1
  • 10
    • 0034226001 scopus 로고    scopus 로고
    • SPEC CPU2000: Measuring CPU performance in the new millennium
    • July
    • J. L. Henning. SPEC CPU2000: Measuring CPU performance in the new millennium. IEEE Computer, 33(7):28-35, July 2000.
    • (2000) IEEE Computer , vol.33 , Issue.7 , pp. 28-35
    • Henning, J.L.1
  • 11
    • 33749395138 scopus 로고
    • Architectural support for reduced register saving/restoring in single-window register files
    • Feb.
    • M. Huguet and T. Lang. Architectural support for reduced register saving/restoring in single-window register files. ACM Trans. Computer Systems, 9(1):66-97, Feb. 1991.
    • (1991) ACM Trans. Computer Systems , vol.9 , Issue.1 , pp. 66-97
    • Huguet, M.1    Lang, T.2
  • 12
    • 20344374162 scopus 로고    scopus 로고
    • Niagara: A 32-way multithreaded spare processor
    • March/April
    • P. Kongetira, K. Aingaran, and K. Olukotun. Niagara: A 32-way multithreaded spare processor. IEEE Micro, 25(2):21-29, March/April 2005.
    • (2005) IEEE Micro , vol.25 , Issue.2 , pp. 21-29
    • Kongetira, P.1    Aingaran, K.2    Olukotun, K.3
  • 25
    • 33749396918 scopus 로고
    • How to use 1000 registers
    • Caltech Computer Science Dept
    • R. L. Sites. How to use 1000 registers. In Caltech Conference on VLSI, pages 527-532. Caltech Computer Science Dept, 1979.
    • (1979) Caltech Conference on VLSI , pp. 527-532
    • Sites, R.L.1
  • 26
    • 0003691648 scopus 로고    scopus 로고
    • R. L. Sites, editor. Digital Press, 3 edition
    • R. L. Sites, editor. Alpha Architecture Reference Manual. Digital Press, 3 edition, 1998.
    • (1998) Alpha Architecture Reference Manual
  • 29
    • 0004328283 scopus 로고
    • D. L. Weaver and T. Germond, editors. PTR Prentice Hall
    • D. L. Weaver and T. Germond, editors. SPARC Architecture Manual (Version 9). PTR Prentice Hall, 1994.
    • (1994) SPARC Architecture Manual (Version 9)


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.