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Volumn , Issue , 2002, Pages 57-66
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Low-complexity reorder buffer architecture
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Author keywords
Low complexity datapath; Low power design; Reorder buffer
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Indexed keywords
BUFFER STORAGE;
COMPUTATIONAL COMPLEXITY;
DATA RECORDING;
ENERGY CONSERVATION;
ENERGY DISSIPATION;
MICROPROCESSOR CHIPS;
LOW-COMPLEXITY RECORDERS;
COMPUTER ARCHITECTURE;
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EID: 0036374205
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1145/514191.514202 Document Type: Conference Paper |
Times cited : (26)
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References (18)
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