Late allocation and early release of physical registers

IEEE Transactions on Computers

Volumn 53, Issue 10, 2004, Pages 1244-1259

  Monreal, Teresa ^a   Viñals, Víctor ^a   González, José ^b   González, Antonio ^c   Valero, Mateo ^c  

^a UNIVERSITY OF ZARAGOZA   (Spain)

^b INTEL CORPORATION   (United States)

^c UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

Out of order processors; Physical register allocation and releasing; Precise exceptions; Register file optimization; Register renaming

Indexed keywords

COMPUTER SIMULATION; PIPELINE PROCESSING SYSTEMS; RESOURCE ALLOCATION; STORAGE ALLOCATION (COMPUTER);

OUT-OF-ORDER PROCESSORS; PHYSICAL REGISTER ALLOCATION; REGISTER FILE OPTIMIZATION; REGISTER RENAMING;

PARALLEL PROCESSING SYSTEMS;

EID: 11944251828     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2004.79     Document Type: Article

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