Interactions between compression and prefetching in chip multiprocessors

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2007, Pages 228-239

  Alameldeen, Alaa R ^a   Wood, David A ^b  

^a INTEL CORPORATION   (United States)

^b University of Wisconsin Madison   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP MULTIPROCESSORS; OFF-CHIP INTERCONNECTS; OFF-CHIP PIN BANDWIDTH; ON-CHIP CACHES;

BANDWIDTH; CACHE MEMORY; COMPUTER HARDWARE; MICROPROCESSOR CHIPS;

MULTIPROCESSING SYSTEMS;

EID: 34547676257     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2007.346200     Document Type: Conference Paper

References (48)

1. Alaa R. Alameldeen. Using Compression to Improve Chip Multiprocessor Performance. PhD thesis, Computer Sciences Department, University of Wisconsin-Madison, 2006.
2. Alaa R. Alameldeen, Milo M. K. Martin, Carl J. Mauer, Kevin E. Moore, Min Xu, Daniel J. Sorin, Mark D. Hill, and David A. Wood. Simulating a S2M Commercial Server on a S2K PC. IEEE Computer, 36(2):50-57, February 2003.
3. Alaa R. Alameldeen and David A. Wood. Variability in Architectural Simulations of Multi-threaded Workloads. In Proc. of the Ninth IEEE Symposium on High-Performance Computer Architecture, pages 7-18, February 2003.
4. Alaa R. Alameldeen and David A. Wood. Adaptive Cache Compression for High-Performance Processors. In Proc. of the 31st Annual International Symposium on Computer Architecture, pages 212-223, June 2004.
5. Vishal Aslot, Max Domeika, Rudolf Eigenmann, Greg Gaertner, Wesley Jones, and Bodo Parady. SPEComp: A New Benchmark Suite for Measuring Parallel Computer Performance. In Workshop on OpenMP Applications and Tools, pages 1-10, July 2001.
6. Paul Barford and Mark Crovella. Generating Representative Web Workloads for Network and Server Performance Evaluation. In Proc. of the 1998 ACM Sigmetrics Conference on Measurement and Modeling of Computer Systems, pages 151-160, June 1998.
7. Bradford M. Beckmann and David A. Wood. Managing Wire Delay in Large Chip-Multiprocessor Caches. In Proc. of the 37th Annual IEEE/ACM International Symposium on Microarchitecture, Dec. 2004.
8. Doug Burger, James R. Goodman, and Alain Kagi. Memory bandwidth limitations of future microprocessors. In Proc. of the 23th Annual International Symposium on Computer Architecture, pages 78-89, May 1996.
9. Ramon Canal, Antonio Gonzalez, and James E. Smith. Very Low Power Pipelines Using Significance Compression. In Proc. of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, pages 181-190, December 2000.
10. David Chen, Enoch Peserico, and Larry Rudolph. A Dynamically Partitionable Compressed Cache. In Proc. of the Singapore-MIT Alliance Symposium, January 2003.
11. Tien-Fu Chen and Jean-Loup Baer. A Performance Study of Software and Hardware Data Prefetching Schemes. In Proc. of the 21st Annual International Symposium on Computer Architecture, pages 223-232, April 1994.
12. Tien-Fu Chen and Jean-Loup Baer. Effective Hardware-Based Data Prefetching for High Performance Processors. IEEE Transactions on Computers, 44(5):609-623, May 1995.
13. Daniel Citron. Exploiting Low Entropy to Reduce Wire Delay. IEEE TCCA Computer Architecture Letters, 3. January 2004.
14. Daniel Citron and Larry Rudolph. Creating a Wider Bus Using Caching Techniques. In Proc. of the First IEEE Symposium on High-Performance Computer Architecture, pages 90-99, February 1995.
15. Fredrik Dahlgren, Michel Dubois, and Per Stenström. Sequential Hardware Prefetching in Shared-Memoiy Multiprocessors. IEEE Transactions on Parallel and Distributed Systems, 6(7):733-746, July 1995.
16. Karel Driesen and Urs Holzle. Accurate Indirect Branch Prediction. In Proc. of the 25th Annual International Symposium on Computer Architecture, pages 167-178, June 1998.
17. Avinoam N. Eden and Trevor Mudge. The YAGS Branch Prediction Scheme. In Proc. of the 25th Annual International Symposium on Computer Architecture, pages 69-77, June 1998.
18. Magnus Ekman and Per Stenstrom. A Robust Main-Memory Compression Scheme. In Proc. of the 32nd Annual International Symposium on Computer Architecture, pages 74-85, June 2005.
19. Matthew Farrens and Arvin Park. Dynamic Base Register Caching: A Technique for Reducing Address Bus Width. In Proc. of the 18th Annual International Symposium on Computer Architecture, pages 128-137, May 1991.
20. Wi fen Lin, Steven K. Reinhardt, and Doug Burger. Reducing DRAM Latencies with an Integrated Memory Hierarchy Design. In Proc. of the Seventh IEEE Symposium on High-Performance Computer Architecture, pages 301-312, January 2001.
21. Brian A. Fields, Rastislav Bodik, Mark D. Hill, and Chris J. Newburn. Using Interaction Costs for Microarchitectural Bottleneck Analysis. In Proc. of the 36th Annual IEEE/ACM International Symposium on Microarchitecture, pages 228-241, December 2003.
22. International Technology Roadmap for Semiconductors. ITRS 2004 Update. Semiconductor Industry Association, 2004. http://www.itrs.net/Common/2004Update/ 2004Update.htm.
23. Erik G. Hallnor and Steven K. Reinhardt. A Compressed Memory Hierarchy using an Indirect Index Cache. Technical ReportCSE-TR-488-04, University of Michigan, 2004.
24. G. Hinton, D. Sager. M. Upton, D. Boggs, D. Carmean, A. Kyker, and P. Roussel. The microarchitecture of the Pentium 4 processor. Intel Technology Journal, February 2001.
25. Tim Horel and Gary Lauterbach. UltraSPARC-III: Designing Third Generation 64-Bit Performance. IEEE Micro, 19(3):73-85, May/June 1999.
26. Jaehyuk Huh, Stephen W. Keckler, and Doug Burger. Exploring the Design Space of Future CMPs. In Proc. of the 2001 International Conference on Parallel Architectures and Compilation Techniques, pages 199-210, 2001.
27. Doug Joseph and Dirk Grunwald. Prefetching Using Markov Predictors. In Proc. of the 24th Annual International Symposium on Computer Architecture, pages 252-263, June 1997.
28. Norman P. Jouppi. Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers. In Proc. of the 17th Annual International Symposium on Computer Architecture, pages 364-373, May 1990.
29. Stephan Jourdan, Tse-Hao Hsing, Jared Stark, and Yale N. Patt. The Effects of Mispredicted-Path Execution on Branch Prediction Structures. In Proc. of the International Conference on Parallel Architectures and Compilation Techniques, pages 58-67, October 1996.
30. Krishna Kant and Ravi Iyer. Compressibility Characteristics of Address/Data transfers in Commercial Workloads. In Proc. of the Fifth Workshop on Computer Architecture Evaluation Using Commercial Workloads, pages 59-67, February 2002.
31. Ando Ki and Alan E. Knowles. Adaptive Data Prefetching Using Cache Information. In Proc. of the 1997 International Conference on Supercomputing, pages 204-212, July 1997.
32. Jang-Soo Lee, Won-Kee Hong, and Shin-Dug Kim. Design and Evaluation of a Selective Compressed Memory System. In Proc. of International Conference on Computer Design (ICCD'99), pages 184-191, October 1999.
33. Jang-Soo Lee, Won-Kee Hong, and Shin-Dug Kim. An On-chip Cache Compression Technique to Reduce Decompression Overhead and Design Complexity. Journal of Systems Architecture:the EUROMICRO Journal, 46(15):1365-1382, December 2000.
34. Jang-Soo Lee, Won-Kee Hong, and Shin-Dug Kim. Adaptive Methods to Minimize Decompression Overhead for Compressed On-chip Cache. International Journal of Computers and Application, 25(2), January 2003.
35. Peter S. Magnusson et al. Simics: A Full System Simulation Platform. IEEE Computer, 35(2):50-58, February 2002.
36. Milo M.K. Martin, Daniel J. Sorin, Bradford M. Beckmann, Michael R. Marty, Min Xu, Alaa R. Alameldeen, Kevin E. Moore, Mark D. Hill, and David A. Wood. Multifacet's General Execution-driven Multiprocessor Simulator (GEMS) Toolset. Computer Architecture News, pages 92-99, September 2005.
37. Alex Pajuelo, Antonio Gonzalez, and Mateo Valero. Speculative Dynamic Vectorization. In Proc. of the 29th Annual International Symposium on Computer Architecture, May 2002.
38. Amir Roth, Andreas Moshovos, and Gurindar S. Sohi. Dependence Based Prefetching for Linked Data Structures. In Proc. of the Eighth International Conference on Architectural Support for Programming Languages and Operating Systems, pages 115-126, Oct. 1998.
39. B. Sinharoy, R.N. Kalla, J.M. Tendler, R.J. Eickemeyer, and J.B. Joyner. Power5 System Microarchitecture. IBM Journal of Research and Development, 49(4), 2005.
40. Viji Srinivasan, Edward S. Davidson, and Gary S. Tyson. A Prefetch Taxonomy. IEEE Transactions on Computers, 53(2):126-140, February 2004.
41. Joel M. Tendler. Steve Dodson, Steve Fields, Hung Le, and Balaram Sinharoy. POWER4 System Microarchitecture. IBM Journal of Research and Development, 46(1), 2002.
42. R.B. Tremaine, P.A. Franaszek, J.T. Robinson, CO. Schulz, T.B. Smith, M.E. Wazlowski, and P.M. Bland. IBM Memory Expansion Technology (MXT). IBM Journal of Research and Development, 45(2):271-285, March 2001.
43. Dean M. Tullsen and Susan J. Eggers. Limitations of Cache Prefetching on a Bus-Based Multiprocessor. In Proc. of the 20th Annual International Symposium on Computer Architecture, pages 278-288, May 1993.
44. Bryan Usevitch. JPEG2000 compliant lossless coding of floating point data. In Proc. of the 2005 Data Compression Conference, page 484. March 2005.
45. Jun Yang, Youtao Zhang, and Rajiv Gupta. Frequent Value Compression in Data Caches. In Proc. of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, pages 258-265, Dec. 2000.
46. Youtao Zhang and Rajiv Gupta. Enabling Partial Cache Line Prefetching Through Data Compression. In Proc. of the 2003 International Conference on Parallel Processing, pages 277-285, Oct. 2003.
47. Youtao Zhang, Jun Yang, and Rajiv Gupta. Frequent Value Locality and Value-centric Data Cache Design. In Proc. of the Ninth International Conference on Architectural Support for Programming Languages and Operating Systems, pages 150-159, November 2000.
48. Zheng Zhang and Josep Torrellas. Speeding up Irregular Applications in Shared-Memory Multiprocessors: Memory Binding and Group Prefetching. In Proc. of the 22nd Annual International Symposium on Computer Architecture, pages 188-199, June 1995.