An on-chip cache compression technique to reduce decompression overhead and design complexity

Journal of Systems Architecture

Volumn 46, Issue 15, 2000, Pages 1365-1382

  Lee, Jang Soo ^a   Hong, Won Kee ^a   Kim, Shin Dug ^a  

^a Yonsei University   (South Korea)

Author keywords

Cache architecture; Compressed memory system; Compression algorithm; Memory hierarchy; Memory performance evaluation; On line data compression

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; HIERARCHICAL SYSTEMS; MICROPROCESSOR CHIPS; STORAGE ALLOCATION (COMPUTER);

COMPRESSED MEMORY SYSTEMS; COMPRESSION ALGORITHMS; SELECTIVE COMPRESSED MEMORY SYSTEMS (SCMS);

BUFFER STORAGE;

EID: 0034499403     PISSN: 13837621     EISSN: None     Source Type: Journal    
DOI: 10.1016/S1383-7621(00)00030-8     Document Type: Article

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