Using interaction costs for microarchitectural bottleneck analysis

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn 2003-January, Issue , 2003, Pages 228-239

  Fields, B A ^a   Bodik R ^a   Hill, M D ^b   Newburn, C J ^c  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b UNIVERSITY OF WISCONSIN MADISON   (United States)

^c INTEL CORPORATION   (United States)

Author keywords

Condition monitoring; Cost function; Delay; Design optimization; Electric breakdown; Hardware; Microarchitecture; Microprocessors; Performance evaluation; Process design

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER HARDWARE; CONDITION MONITORING; COST FUNCTIONS; COSTS; DESIGN; ELECTRIC BREAKDOWN; HARDWARE; INTEGRATED CIRCUIT DESIGN; MICROPROCESSOR CHIPS; PARALLEL PROCESSING SYSTEMS; PROCESS DESIGN;

BOTTLENECK ANALYSIS; DELAY; DESIGN OPTIMIZATION; HARDWARE STRUCTURES; MICRO ARCHITECTURES; MODERN PROCESSORS; PERFORMANCE EVALUATION; PERFORMANCE MONITORING;

COST BENEFIT ANALYSIS;

EID: 27544512320     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2003.1253198     Document Type: Conference Paper

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