Enabling partial cache line prefetching through data compression

Proceedings of the International Conference on Parallel Processing

Volumn 2003-January, Issue , 2003, Pages 277-285

  Zhang, Y ^a   Gupta, R ^b  

^a The University of Texas at Dallas   (United States)

^b University of Arizona   (United States)

Author keywords

Bandwidth; Computer science; Data compression; Delay; Hardware; High performance computing; Parallel processing; Pipelines; Pollution; Prefetching

Indexed keywords

BANDWIDTH; BANDWIDTH COMPRESSION; CACHE MEMORY; COMPUTER HARDWARE; COMPUTER SCIENCE; HARDWARE; PIPELINE PROCESSING SYSTEMS; PIPELINES; POLLUTION;

DELAY; HIGH PERFORMANCE COMPUTING; MEMORY HIERARCHY; PARALLEL PROCESSING; PRE-FETCHING SCHEME; PREFETCHING; PROGRAM EXECUTION; SIMPLE COMPRESSIONS;

DATA COMPRESSION;

EID: 84944720428     PISSN: 01903918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICPP.2003.1240590     Document Type: Conference Paper

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