A compressed memory hierarchy using an indirect index cache

ACM International Conference Proceeding Series

Volumn 68, Issue , 2004, Pages 9-15

  Hallnor, Erik G ^a   Reinhardt, Steven K ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUS BANDWIDTH; BUS TRANSFER; CACHE CAPACITY; CACHE DESIGN; CACHE SIZE; COMPRESSED STATE; DIE AREA; EFFECTIVE BANDWIDTH; EFFECTIVE CAPACITY; EFFECTIVE SIZE; HIDING MEMORY LATENCY; MAIN MEMORY; MEMORY BUS; MEMORY HIERARCHY; MEMORY LATENCIES; MEMORY STRUCTURE; SIMULATION RESULT; SYSTEM EFFICIENCY; TRANSMITTING DATA;

BANDWIDTH; BUSES; COMPUTER ARCHITECTURE; COMPUTERS; DESIGN;

CACHE MEMORY;

EID: 77954443981     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1054943.1054945     Document Type: Conference Paper

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