-
1
-
-
0004328283
-
-
Prentice Hall, Englewood Cliffs, N.J.
-
D. Weaver and T. Germond, The SPARC Architecture Manual, Version 9, Prentice Hall, Englewood Cliffs, N.J., 1994.
-
(1994)
The SPARC Architecture Manual, Version 9
-
-
Weaver, D.1
Germond, T.2
-
2
-
-
0004868449
-
-
Tech. Report TR-95-44, Sun Laboratories, Mountain View, Calif.
-
N. Wilhelm, "Why Wire Delays Will No Longer Scale for VLSI Chips," Tech. Report TR-95-44, Sun Laboratories, Mountain View, Calif., 1995.
-
(1995)
Why Wire Delays Will No Longer Scale for VLSI Chips
-
-
Wilhelm, N.1
-
3
-
-
0344938648
-
-
Tech. Report CSL-TR-94-615, Stanford University, Stanford, Calif.
-
K.J. Nowka and M.J. Flynn, Wave Pipelining of High-Performance CMOS Static RAM, Tech. Report CSL-TR-94-615, Stanford University, Stanford, Calif., 1994.
-
(1994)
Wave Pipelining of High-Performance CMOS Static RAM
-
-
Nowka, K.J.1
Flynn, M.J.2
-
4
-
-
0026918390
-
Improving branch prediction accuracy using branch correlation
-
ACM Press, New York
-
S.-T. Pan, K. So, and J. Rameh, "Improving Branch Prediction Accuracy using Branch Correlation," Proc. Fifth Conf. Architectural Support for Programming Languages and Operating Systems, ACM Press, New York, 1992, pp. 76-84.
-
(1992)
Proc. Fifth Conf. Architectural Support for Programming Languages and Operating Systems
, pp. 76-84
-
-
Pan, S.-T.1
So, K.2
Rameh, J.3
-
6
-
-
0032204698
-
64-KByte sum-addressed-memory cache with 1.6-ns cycle and 2.6ns latency
-
Nov.
-
R. Heald et al., "64-KByte Sum-Addressed-Memory Cache with 1.6-ns Cycle and 2.6ns Latency," IEEE J. Solid-State Circuits, Nov. 1998, pp. 1,682-1,689.
-
(1998)
IEEE J. Solid-State Circuits
, pp. 1682-1689
-
-
Heald, R.1
-
7
-
-
0025429331
-
Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers
-
IEEE Computer Soc. Press, Los Alamitos, Calif.
-
N. Jouppi, "Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers," Proc. 17th Ann. Int'l Symp. Computer Architecture, IEEE Computer Soc. Press, Los Alamitos, Calif., 1990, pp. 364-373.
-
(1990)
Proc. 17th Ann. Int'l Symp. Computer Architecture
, pp. 364-373
-
-
Jouppi, N.1
-
8
-
-
0026267802
-
An effective on-chip preloading scheme to reduce data access penalty
-
IEEE Computer Soc. Press
-
J.-L. Baer and T.-F. Chen,"An Effective On-Chip Preloading Scheme to Reduce Data Access Penalty," Proc. Supercomputing 91, IEEE Computer Soc. Press, 1991, pp. 176-186.
-
(1991)
Proc. Supercomputing 91
, pp. 176-186
-
-
Baer, J.-L.1
Chen, T.-F.2
-
10
-
-
0345369961
-
A non-blocking multiple-phase clocking scheme for dynamic logic
-
IEEE Press, Piscataway, N.J.
-
F. Klass, "A Non-Blocking Multiple-Phase Clocking Scheme for Dynamic Logic," IEEE Int'l Workshop on Clock Distribution Networks Design, Synthesis, and Analysis, IEEE Press, Piscataway, N.J., 1997.
-
(1997)
IEEE Int'l Workshop on Clock Distribution Networks Design, Synthesis, and Analysis
-
-
Klass, F.1
-
11
-
-
0031640603
-
Semi-dynamic and dynamic flip-flops with embedded logic
-
Digest of Tech. Papers, IEEE Press
-
F. Klass, "Semi-dynamic and Dynamic Flip-flops with Embedded Logic." Digest of Tech. Papers, 1998 Symp. VLSI Circuits, IEEE Press, 1998, pp. 108-109.
-
(1998)
1998 Symp. VLSI Circuits
, pp. 108-109
-
-
Klass, F.1
|