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Volumn 19, Issue 3, 1999, Pages 73-85

UltraSPARC-III: designing third-generation 64-bit performance

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BUFFER STORAGE; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; COMPUTER WORKSTATIONS; DATA STRUCTURES; DIGITAL ARITHMETIC; INTEGER PROGRAMMING; INTERFACES (COMPUTER); PERSONAL COMPUTERS; PIPELINE PROCESSING SYSTEMS; SYSTEMS ANALYSIS;

EID: 0032630821     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/40.768506     Document Type: Article
Times cited : (92)

References (11)
  • 6
    • 0032204698 scopus 로고    scopus 로고
    • 64-KByte sum-addressed-memory cache with 1.6-ns cycle and 2.6ns latency
    • Nov.
    • R. Heald et al., "64-KByte Sum-Addressed-Memory Cache with 1.6-ns Cycle and 2.6ns Latency," IEEE J. Solid-State Circuits, Nov. 1998, pp. 1,682-1,689.
    • (1998) IEEE J. Solid-State Circuits , pp. 1682-1689
    • Heald, R.1
  • 7
    • 0025429331 scopus 로고
    • Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers
    • IEEE Computer Soc. Press, Los Alamitos, Calif.
    • N. Jouppi, "Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers," Proc. 17th Ann. Int'l Symp. Computer Architecture, IEEE Computer Soc. Press, Los Alamitos, Calif., 1990, pp. 364-373.
    • (1990) Proc. 17th Ann. Int'l Symp. Computer Architecture , pp. 364-373
    • Jouppi, N.1
  • 8
    • 0026267802 scopus 로고
    • An effective on-chip preloading scheme to reduce data access penalty
    • IEEE Computer Soc. Press
    • J.-L. Baer and T.-F. Chen,"An Effective On-Chip Preloading Scheme to Reduce Data Access Penalty," Proc. Supercomputing 91, IEEE Computer Soc. Press, 1991, pp. 176-186.
    • (1991) Proc. Supercomputing 91 , pp. 176-186
    • Baer, J.-L.1    Chen, T.-F.2
  • 11
    • 0031640603 scopus 로고    scopus 로고
    • Semi-dynamic and dynamic flip-flops with embedded logic
    • Digest of Tech. Papers, IEEE Press
    • F. Klass, "Semi-dynamic and Dynamic Flip-flops with Embedded Logic." Digest of Tech. Papers, 1998 Symp. VLSI Circuits, IEEE Press, 1998, pp. 108-109.
    • (1998) 1998 Symp. VLSI Circuits , pp. 108-109
    • Klass, F.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.