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Volumn 1, Issue , 2006, Pages

Reuse-based test access and integrated test scheduling for network-on-chip

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; COMPUTATIONAL COMPLEXITY; COMPUTER HARDWARE; COMPUTER SOFTWARE REUSABILITY; NETWORK MANAGEMENT; RESOURCE ALLOCATION; ROUTERS;

EID: 34047171406     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (22)

References (18)
  • 1
    • 0036143962 scopus 로고    scopus 로고
    • A Complete Strategy for Testing an On-Chip Multiprocessor Architecture
    • Jan-Feb
    • C. Aktouf. A Complete Strategy for Testing an On-Chip Multiprocessor Architecture. IEEE Design & Test of Computers, vol. 19, pp. 18-28, Jan-Feb 2002.
    • (2002) IEEE Design & Test of Computers , vol.19 , pp. 18-28
    • Aktouf, C.1
  • 2
  • 3
    • 0036693853 scopus 로고    scopus 로고
    • CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing
    • Aug
    • M. Benabdenbi, W. Maroufi, and M. Marzouki. CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing. Journal of Electronic Testing: Theory and Applications, vol. 18, pp. 455-473, Aug. 2002.
    • (2002) Journal of Electronic Testing: Theory and Applications , vol.18 , pp. 455-473
    • Benabdenbi, M.1    Maroufi, W.2    Marzouki, M.3
  • 4
    • 3042613418 scopus 로고    scopus 로고
    • System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip
    • A. Bona, V. Zaccaria and R. Zafalon. System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip. Proc. Design, Automation and Test in Europe, pp. 318-323, 2004.
    • (2004) Proc. Design, Automation and Test in Europe , pp. 318-323
    • Bona, A.1    Zaccaria, V.2    Zafalon, R.3
  • 7
    • 0034848112 scopus 로고    scopus 로고
    • Route Packets, Not Wires: On-Chip Interconnection Networks
    • W. J. Dally and B. Towles. Route Packets, Not Wires: On-Chip Interconnection Networks. Proc. Design Automation Conference, pp. 684-689, 2001.
    • (2001) Proc. Design Automation Conference , pp. 684-689
    • Dally, W.J.1    Towles, B.2
  • 8
    • 0002515893 scopus 로고    scopus 로고
    • Cluster-based Test Architecture Design for System-on-Chip
    • S. Goel and E. Marinissen. Cluster-based Test Architecture Design for System-on-Chip. Proc. IEEE VLSI Test Symposium, pp. 259-264, 2002.
    • (2002) Proc. IEEE VLSI Test Symposium , pp. 259-264
    • Goel, S.1    Marinissen, E.2
  • 11
    • 0142215922 scopus 로고    scopus 로고
    • A Reconfigurable Power-Conscious Core Wrapper and Its Application to SOC Test Scheduling
    • E. Larsson and Z. Peng. A Reconfigurable Power-Conscious Core Wrapper and Its Application to SOC Test Scheduling. Proc. International Test Conference, pp. 1135-1144, 2003.
    • (2003) Proc. International Test Conference , pp. 1135-1144
    • Larsson, E.1    Peng, Z.2
  • 12
    • 18144395845 scopus 로고    scopus 로고
    • Test Scheduling for Network-on-Chip with BIST and Precedence Constraints
    • C. Liu et al. Test Scheduling for Network-on-Chip with BIST and Precedence Constraints. Proc. International Test Conference, pp. 1369-1378, 2004.
    • (2004) Proc. International Test Conference , pp. 1369-1378
    • Liu, C.1
  • 13
    • 0036443045 scopus 로고    scopus 로고
    • E. J. Marinissen, V. Iyengar, and K. Chakrabarty. A Set of Benchmarks for Modular Testing of SOCs. Proc. International Test Conference, pp. 521-528, 2002.
    • E. J. Marinissen, V. Iyengar, and K. Chakrabarty. A Set of Benchmarks for Modular Testing of SOCs. Proc. International Test Conference, pp. 521-528, 2002.
  • 15
    • 0011840160 scopus 로고    scopus 로고
    • A Packet Switching Communication-based Test Access Mechanism for System Chips
    • M. Nahvi and A. Ivanov. A Packet Switching Communication-based Test Access Mechanism for System Chips. Proc. IEEE European Test Workshop, pp. 81-86, 2001.
    • (2001) Proc. IEEE European Test Workshop , pp. 81-86
    • Nahvi, M.1    Ivanov, A.2
  • 17
    • 0141517360 scopus 로고    scopus 로고
    • Bringing Communication Networks On-Chip: The Test and Verification Implications
    • Sept
    • B. Vermeulen, J. Dielissen, K. Goossens, and C. Ciordas. Bringing Communication Networks On-Chip: The Test and Verification Implications. IEEE Communications Magazine, vol. 41, pp. 74-81, Sept. 2003.
    • (2003) IEEE Communications Magazine , vol.41 , pp. 74-81
    • Vermeulen, B.1    Dielissen, J.2    Goossens, K.3    Ciordas, C.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.