Low-power design of pipeline A/D converters

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2006, Pages 505-512

  Kawahito, S ^a  

^a SHIZUOKA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POWER UTILIZATION; OPTIMIZATION; PARALLEL PROCESSING SYSTEMS;

MULTIPLE-STAGE PIPELINE; PARALLEL-PIPELINE ARCHITECTURES;

ANALOG TO DIGITAL CONVERSION;

EID: 33947634483     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2006.320894     Document Type: Conference Paper

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