A 90nm CMOS 1.2V 10b power and speed programmable pipelined ADC with 0.5pJ/conversion-step

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2006, Pages

  Geelen, Govert ^a   Paulus, Edward ^a   Simanjuntak, Dobson ^a   Pastoor, Hein ^a   Verlinden, René ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; FREQUENCY CONVERTER CIRCUITS; NATURAL FREQUENCIES; PIPELINE PROCESSING SYSTEMS; POWER ELECTRONICS; SAMPLING;

POWER EFFICIENCY; SAMPLING FREQUENCIES; SUPPLY VOLTAGE;

ANALOG TO DIGITAL CONVERSION;

EID: 33847730791     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. M. Yoshioka, et al., "A 10b 125MS/S 40mW Pipelined ADC in 0.18μm CMOS," ISSCC Dig. Tech. Papers, pp. 282-283, Feb., 2005.
2. O. Stroeble, V. Dias, C. Schwoerer, "An 80MHz 10b Pipeline ADC with Dynamic Range Doubling and Dynamic Reference Selection," ISSCC Dig. Tech. Papers, pp. 462-463, Feb., 2004.
3. B. Min, et al., "A 69-mW 10-bit 80-MSample/s Pipelined CMOS ADC," IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2031-2039, Dec., 2003.
4. D. Miyazaki, S. Kawahito, M. Furuta, "A 10-b 30-MS/s Low-Power Pipelined CMOS A/D Converter Using a Pseudodifferential Architecture," IEEE J. Solid-State Circuits, vol. 38, no. 2, pp. 369-373, Feb., 2003.
5. B. Hernes, et al., "A 1.2V 220MS/S 10b Pipeline ADC Implemented in 0.13μm Digital CMOS," ISSCC Dig. Tech. Papers, pp. 256-257, Feb., 2004.