A digital calibration technique of capacitor mismatch for pipelined analog-to-digital converters

IEICE Transactions on Electronics

Volumn E85-C, Issue 8, 2002, Pages 1562-1568

  Masanori, Furuta ^a   Shoji, Kawahito ^a   Daisuke, Miyazaki ^a  

^a SHIZUOKA UNIVERSITY   (Japan)

Author keywords

Digital calibration; Error measurement; Parallel pipelined ADC; Pipelined ADC

Indexed keywords

ALGORITHMS; ANALOG TO DIGITAL CONVERSION; APPROXIMATION THEORY; CALCULATIONS; CAPACITORS; COMPARATOR CIRCUITS; DIFFERENTIAL AMPLIFIERS; DIGITAL CIRCUITS; ERROR ANALYSIS; GRAPH THEORY; MATHEMATICAL MODELS; SIGNAL TO NOISE RATIO;

DIFFERENTIAL NON-LINEARITY; DIGITAL CALIBRATION TECHNIQUE; ERROR MEASUREMENT; INTEGRAL NON-LINEARITY;

ERROR CORRECTION;

EID: 0036670375     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (7)

1. A 10-bit 200-MS/s CMOS parallel pipelined A/D converter
2. A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3 μm CMOS
3. A low-power 12-b analog-to-digital converter with on-chip precision trimming
4. A digital background calibration technique for time-interleaved analog-to-digital converters
5. A single-ended 12-bit 20 Msample/s self-calibrating pipelined A/D converter
6. A 12-b 600 ks/s digitally self-calibrated pipelined algorithmic ADC
7. A switched current, switched capacitor temperature sensor in 0.6 μ CMOS