A 1V 30mW 10b 100MSample/s pipeline A/D converter using capacitance coupling techniques

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2006, Pages 224-225

  Honda, Kazutaka ^a   Masanori, Furuta ^a   Kawahito, Shoji ^a  

^a SHIZUOKA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; ENERGY DISSIPATION; POWER SUPPLY CIRCUITS;

CAPACITANCE COUPLING TECHNIQUES; POWER SUPPLY;

ANALOG TO DIGITAL CONVERSION;

EID: 39749182258     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. A. M. Abo and P. R. Gray, "A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter," IEEE JSSC, vol. 34, pp. 599 - 606, May 1999.
2. M. Waltari and K. A. I. Halonen, "1-V 9-Bit Pipelined Switched-Opamp ADC," IEEE JSSC, vol. 36, pp. 129-134, Jan. 2001.
3. D. Miyazaki, M. Furuta, andS. Kawahito, "A 16mW 30MSample/s 10b Pipeline A/D Converter Using Pseudo Differencial Architecture," IEEE ISSCC Dig. Tech. Papers, pp. 174-175, Feb. 2002.
4. M.Yoshioka, M. Kudo, K. Gotoh, and Y. Watanabe, "A 10b 125MS/S 40mW Pipelined ADC in 0.18μm CMOS," IEEE ISSCC Dig. Tech. Papers, pp. 282-283, Feb. 2005.