Low-power design of high-speed A/D converters

IEICE Transactions on Electronics

Volumn E88-C, Issue 4, 2005, Pages 468-478

  Kawahito, Shoji ^a,b,c   Honda, Kazutaka ^a   Furuta, Masanori ^a   Kawai, Nobuhiro ^a,d   Miyazaki, Daisuke ^a  

^a SHIZUOKA UNIVERSITY   (Japan)

^b International Society for Optical Engineering   (Japan)

^c Institute of Electrical and Electronic Engineers   (Japan)

^d Institute of Image Information and Television Engineers of Japan   (Japan)

Author keywords

Low power design; Parallel pipeline ADC; Pipeline ADC; Power optimization

Indexed keywords

OPTIMIZATION; SAMPLING; SIGNAL TO NOISE RATIO; SPURIOUS SIGNAL NOISE;

LOW-POWER DESIGN; PARALLEL-PIPELINE ADC; PIPELINE ADC; POWER OPTIMIZATION;

ANALOG TO DIGITAL CONVERSION;

EID: 33645573541     PISSN: 09168524     EISSN: 17451353     Source Type: Journal    
DOI: 10.1093/ietele/e88-c.4.468     Document Type: Article

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