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Volumn , Issue , 2004, Pages 631-637

Perspectives on scaling theory and CMOS technology - Understanding the past, present, and future

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EID: 27644541823     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (2)

References (16)
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  • 3
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    • Fundamental limitations in microelectronics - I. MOS technology
    • C. Mead, "Fundamental Limitations in Microelectronics - I. MOS Technology," Sol. St. Elec. vol. 15, pp. 819-829 (1972).
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    • Mead, C.1
  • 4
    • 0016116644 scopus 로고
    • Design of ion implanted MOSFETs with very small physical dimensions
    • R. Dennard et al., "Design of Ion Implanted MOSFETs with Very Small Physical Dimensions," IEEE J. Sol. St. Circ. vol. SC-9, pp. 256 - 268 (1974).
    • (1974) IEEE J. Sol. St. Circ. , vol.SC-9 , pp. 256-268
    • Dennard, R.1
  • 5
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    • Ultimate CMOS ULSI Performance
    • E. Nowak, "Ultimate CMOS ULSI Performance," 1993 IEDM Tech. Dig., pp. 115-118.
    • 1993 IEDM Tech. Dig. , pp. 115-118
    • Nowak, E.1
  • 6
    • 0028447782 scopus 로고
    • MOSFET technology for low voltage/low power applications
    • June
    • D. Foty and E. Nowak, "MOSFET Technology for Low Voltage/Low Power Applications," IEEE Micro, June 1994, pp. 68-77.
    • (1994) IEEE Micro , pp. 68-77
    • Foty, D.1    Nowak, E.2
  • 8
    • 84907697412 scopus 로고    scopus 로고
    • Performance, reliability, and supply voltage reduction, with the addition of temperature as a design variable
    • D. Foty and E. Nowak, "Performance, Reliability, and Supply Voltage Reduction, with the Addition of Temperature as a Design Variable," Proceedings of the 1993 European Solid State Device Research Conference, pp. 943-948.
    • Proceedings of the 1993 European Solid State Device Research Conference , pp. 943-948
    • Foty, D.1    Nowak, E.2
  • 9
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    • Moderate inversion in MOS devices
    • Y. Tsividis, "Moderate Inversion in MOS Devices," Sol. St. Elec. Vol. 25, pp. 1099-1104 (1982).
    • (1982) Sol. St. Elec. , vol.25 , pp. 1099-1104
    • Tsividis, Y.1
  • 12
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    • A CAD methodology for optimizing transistor current and sizing in analog CMOS design
    • D. Binkley et al., "A CAD Methodology for Optimizing Transistor Current and Sizing in Analog CMOS Design," IEEE Transactions on Computer-Aided Design of Circuits and Systems vol. CAD-22, pp. 225-237 (2003).
    • (2003) IEEE Transactions on Computer-aided Design of Circuits and Systems , vol.CAD-22 , pp. 225-237
    • Binkley, D.1
  • 13
    • 0029342165 scopus 로고
    • An analytical MOS transistor model valid in all regions of operation and dedicated to low voltage and low current applications
    • C. Enz, F. Krummenacher, and E. Vittoz, "An Analytical MOS Transistor Model Valid in All Regions of Operation and Dedicated to Low Voltage and Low Current Applications," Analog Int. Circ. and Signal Proc. vol. 8, pp 83-114 (1995).
    • (1995) Analog Int. Circ. and Signal Proc. , vol.8 , pp. 83-114
    • Enz, C.1    Krummenacher, F.2    Vittoz, E.3
  • 14
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    • An advanced surface-potential-based compact MOSFET model
    • in press
    • G. Gildenblat et al., "An Advanced Surface-Potential-Based Compact MOSFET Model," IEEE J. Sol. St. Circ. (in press).
    • IEEE J. Sol. St. Circ.
    • Gildenblat, G.1
  • 15
    • 0024088911 scopus 로고
    • Temperature-scaling theory for low-temperature-operated MOSFET with deep-submicron channel
    • Y. Yi et al., "Temperature-Scaling Theory for Low-Temperature- Operated MOSFET with Deep-Submicron Channel," Jpn. J. Appl. Phys. vol. 27, pp. L1958-L1961 (1988).
    • (1988) Jpn. J. Appl. Phys. , vol.27
    • Yi, Y.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.