Impact of intercluster communication mechanisms on ILP in clustered VLIW architectures

ACM Transactions on Design Automation of Electronic Systems

Volumn 12, Issue 1, 2007, Pages

  Gangwar, Anup ^a,c   Balakrishnan, M ^b   Kumar, Anshul ^b  

^a FREESCALE SEMICONDUCTOR INC   (United States)

^b INDIAN INSTITUTE OF TECHNOLOGY DELHI   (India)

^c Freescale Semiconductor India Pvt Ltd   (India)

Author keywords

ASIP; Clustered VLIW processors; Performance evaluation; VLIW

Indexed keywords

EID: 33847003719     PISSN: 10844309     EISSN: 15577309     Source Type: Journal    
DOI: 10.1145/1217088.1217089     Document Type: Article

References (39)

1. ADITYA, S., KATHAIL, V., AND RAU, B. R. 1998. Elcor's machine description system: Version 3.0. Tech. rep. HPL- 1998-128. Hewlett-Packard Laboratories, Palo Alto, CA.
2. BANERJIA, S., HAVANKI, W. A., AND CONTE, T. M. 1997. Treegion scheduling for highly parallel processors. In Proceedings of the European Conference on Parallel Processing. 1074-1078.
3. BHARGAVA, R. AND JOHN, L. K. 2003. Improving dynamic cluster assignment for clustered trace cache processors. In Proceedings of the 30th Annual International Symposium on Computer Architecture. 264-274.
4. HANG, P. P., MAHLKE, S. A., CHEN, W. Y., WARTER, N. J., AND Hwu, W. W. 1991. IMPACT: An architectural framework for multiple-instruction-issue processors. ACM Comput. Architect. News 19, 3, 266-275.
5. ODINA, J. M., SANCHEZ, J., AND GONZALEZ, A. 2001. A unified modulo scheduling and register allocation technique for clustered processors. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT 2001).
6. RUZ, J.-L., GONZALEZ, A., AND VALERO, M. 2000. Multiple-banked register file architectures. In Proceedings of the International Symposium on Computer Architecture (ISCA- 2000).
7. ESOLI, G. 1998. Instruction assignment for clustered VLIW DSP compilers: A new approach. Tech. rep. HPL- 98-13. Hewlett-Packard Laboratories, Palt Alto, CA.
8. FARABOSCHI, P., BROWN, G., FISHER, J. A., DESOLI, G., AND HOMEWOOD, F. M. O. 2000. Lx: A technology platform for customizable VLIW embedded processing. In Proceedings of the International Symposium on Computer Architecture (ISCA'2000). ACM Press, New York, NY.
9. FISHER, J. A., FARABOSCHI, P., AND DESOLI, G. 1996. Custom-fit processors: Letting applications define architectures. In Proceedings of the IEEE Symposium on Microarchitectures.
10. FRITTS, J. AND MANGIONE-SMITH, B. 2002. MediaBench II - technology, status, and cooperation. In Proceedings of the Workshop on Media and Stream Processors (Istanbul, Turkey).
11. FRITTS, J. AND WOLF, W. 2000. Evaluation of static and dynamic scheduling for media processors. In Proceedings of the 2nd Workshop on Media Processors and DSPs in Conjunction with 33rd Annual International Symposium on Microarchitecture. ACM Press, New York, NY.
12. FRITTS, J., WU, Z., AND WOLF, W. 1999. Parallel media processors for the billion-transistor era. In Proceedings of the International Conference on Parallel Processing. 354-362.
13. GANGWAR, A., BALAKRISHNAN, M., PANDA, P. R., AND KUMAR, A. 2005. Evaluation of bus based interconnect mechanisms in clustered VLIW architectures. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE-2005). 730-735.
14. HWU, W. W., MAHLKE, A., S., CHEN, W. Y., CHANG, P. P., WARTER, N. J., BRINGMANN, R. A., OUELLETTE, R. G., HANK, R. E., KIYOHARA, T., HAAB, G. E., HOLM, J. G., AND LAVERY, D. M. 1993. The Superblock: An effective technique for VLIW and superscalar compilation. J. Supercomput 7, 1-2, 229-248.
15. JACOME, M. AND DE VECIANA, G. 2000. Design challenges for new application specific processors. In IEEE Design and Test of Computers. Number 2. 40-50.
16. JACOME, M. F., DE VECIANA, G., AND LAPINSKII, V. 2000. Exploring performance tradeoffs for clustered VLIW ASIPs. In Proceedings of the IEEE / ACM International Conference on Computer-Aided Design (ICCAD' 2000).
17. KAILAS, K., EBCIOGLU, K., AND AGRAWALA, A. K. 2001. CARS: A new code generation framework for clustered ILP processors. In Proceedings of the HPCA. 133-144.
18. KOZYRAKIS, C. E., PERISSAKIS, S., PATTERSON, D., ANDERSON, T., ASANOVIC, K., CARDWELL, N., FROMM, R., GOLBUS, J., GRIBSTAD, B., KEETON, K., THOMAS, R., TREUHAFT, N., AND YELICK, K. 1997. Scalable processors in the billion-transistor era: IRAM. IEEE Comput. 30, 9 (Sept.), 75-78.
19. APINSKII, V., JACOME, M. F., AND DE VECIANA, G. 2001. High quality operation binding for clustered VLIW datapaths. In Proceedings of the IEEE / ACM Design Automation Conference (DAC' 2001).
20. EE, C., POTKONJAK, M., AND MANGIONK- SMITH, W. H. 1997. Mediabench: A tool for evaluating and synthesizing multimedia and communicatons systems. In Proceedings of the International Symposium on Microarchitecture. 330-335.
21. EE, H.-H., Wu, Y., AND TYSON, G. 2000. Quantifying instruction-level parallelism limits on an EPIC architecture. In Proceedings of the International Symposium on Performance Analysis of Systems and Software.
22. EE, W., BARUA, R., FRANK, M., SRIKRISHNA, D., BABB, J., SARKAR, V., AND AMARASINGHE, S. P. 1998. Space-time scheduling of instruction-level parallelism on a raw machine. In Proceedings of the Conference on Architectural Support for Programming Languages and Operating Systems, 46-57.
23. EUPERS, R. 2000. Instruction scheduling for clustered VLIW DSPs. In Proceedings of the IEEE PACT. 291-300.
24. EWIS, D., GALLOWAY, D., IERSSEL, M., ROSE, J., AND CHOW, P. 1997. The transmogrifier-2: A 1-million gate rapid prototyping system. In Proceedings of the ACM 5th International Symposium on Field Programmable-Gate Arrays. Monterey, CA. 53-61.
25. AHLKE, S. A., LIN, D. C., CHEN, W. Y., HANK, R. E., AND BRINGMANN, R. A. 1992. Effective compiler support for predicated execution using the hyperblock. In Proceedings of the 25th Annual International Symposium on Microarchitecture.
26. ATTSON, P., DALLY, W. J., RIXNER, S., KAPASI, U. J., AND OWENS, J. D. 2001. Communication scheduling. In Proceedings of the Ninth International Conference on Architectural Support for Programming Languages and Operating System. 82-92.
27. OZER, E., BANERJIA, S., AND CONTE, T. M. 1998. Unified assign and schedule: A new approach to scheduling for clustered register file microarchitectures. In Proceedings of the International Symposium on Microarchitecture. 308-315.
28. RIXNER, S., DALLY, W. J., KHAILANY, B., MATTSON, P. R., KAPASI, U. J., AND OWENS, J. D. 2000. Register organization for media processing. In Proceedings of 6th International Symposium on High Performance Computer Architecture. 375-386.
29. SANCHEZ, J., GIBERT, E., AND GONZALEZ, A. 2002. An interleaved cache clustered VLIW processor. In Proceedings of the ACM International Conference on Supercomputing (ICS' 2002).
30. SANCHEZ, J. AND GONZALEZ, A. 2000. Instruction scheduling for clustered VLIW architectures. In Proceedings of the International Symposium on System, Synthesis (ISSS' 2000).
31. SIROYAN. 2002. Go online to http://www.siroyan.com.
32. SMITS, J. E. 2001. Instruction-level distributed processing. IEEE Comput. 34, 4 (Apr.), 59-65.
33. SONG, P. 1998. Demystifying EPIC and IA-64. Microprocessor Report, vol. 12, no. 1.
34. STEFANOVIC, D. AND MARTONOSI, M. 2001. Limits and graph structure of available instruction-level parallelism (research note). In Euro-Par 2000 Parallel Processing, A. Bode, T. Ludwig, W. Karl, and R. Wismueller, Eds. Lecture Notes in Computer Science, vol. 1900. Springer-Verlag, Berlin, Germany, 1018-1022.
35. TERECHKO, A., THENAFF, E. L., GARG, M., VAN EIJNDHOVEN, J., AND CORPORAAL, H. 2003. Inter-cluster communication models for clustered VLIW processors. In Proceedings of the 9th International Symposium on High Performance Computer Architecture (Anaheim, CA). 298-309.
36. TEXAS INSTRUMENTS. 2000. TMS3206000 CPU and Instruction Set Reference Guide. Texas Instruments, Dallas, TX.
37. TRIMARAN CONSORTIUM. 1998. The trimaran compiler infrastructure. Go online to http://www.trimaran.org.
38. ZALAMEA, J., LLOSA, J., AYGUADE, E., AND VALERO, M. 2001. Modulo scheduling with integrated register spilling for clustered VLIW architectures. In Proceedings of the 34th Annual ACM / IEEE International Symposium on Microarchitecture. 160-169.
39. ZIVOJINOVIC, V., VELARDE, J. M., SCHLAGER, C., AND MEYR, H. 1994. DSPStone - a DSP-oriented benchmarking methodology. In Proceedings of the International Conference on Signal Processing Application Technology (Dallas, TX). 715-720.