Limits and graph structure of available instruction-level parallelism

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1900, Issue , 2000, Pages 1018-1022

  Stefanović, Darko ^a   Martonosi, Margaret ^a  

^a PRINCETON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA FLOW GRAPHS; DATA TRANSFER; GRAPHIC METHODS; VERY LONG INSTRUCTION WORD ARCHITECTURE;

GRAPH STRUCTURES; INSTRUCTION LEVEL PARALLELISM; INSTRUCTION STREAMS; OPTIMIZING COMPILERS; RUNTIMES; STRUCTURE ANALYSIS; SUPERSCALAR;

DATA FLOW ANALYSIS;

EID: 84937424966     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-44520-x_144     Document Type: Conference Paper

References (14)

1. T. M. Austin and G. S. Sohi. Dynamic dependency analysis of ordinary programs. In 19th ISCA, pages 342–351, May 1992.
2. J. W. Davidson and S. Jinturkar. Improving instruction-level parallelism by loop unrolling and dynamic memory disambiguation. In MICRO-28, Dec. 1995.
3. A. Nicolau and J. A. Fisher. Measuring the parallelism available for very long instruction word architectures. IEEE Trans. Comput., C-33(11):968–976, Nov. 1984.
4. D. W. Wall. Limits of instruction-level parallelism. WRL Research Report 93/6, Digital Equipment Corporation, Western Research Laboratory, Palo Alto, CA, Nov. 1993.
5. C. C. Foster and E. M. Riseman. Percolation of code to enhance parallel dispatching and execution. IEEE Trans. Comput., C-21(12):1411–1415, Dec. 1972.
6. N. P. Jouppi. The nonuniform distribution of instruction-level and machine parallelism and its effect on performance. IEEE Trans. Comput., 38(12):1645–1658, Dec. 1989.
7. M. D. Smith, M. Johnson, and M. A. Horowitz. Limits on multiple instruction issue. In ASPLOS III, pages 290–302, Boston, Massachusetts, 1989.
8. M. Butler, T.-Y. Yeh, Y. Patt, M. Alsup, H. Scales, and M. Shebanow. Single instruction stream parallelism is greater than two. In 18th ISCA, pages 276–286, May 1991.
9. M. S. Lam and R. P. Wilson. Limits of control flow on parallelism. In 19th ISCA, pages 46–57, May 1992.
10. M. A. Postiff, D. A. Greene, G. S. Tyson, and T. N. Mudge. The limits of instructions level parallelism in SPEC95 applications. In 3rd Workshop on Interaction Between Compilers and Computer Architecture, Oct. 1998.
11. J. L. Hennessy and D. A. Patterson. Computer Architecture: A Quantitative Approach. Morgan Kaufman Publishers, Inc., San Mateo, California, 1996. Second Edition.
12. K. Ebcioǧlu, E. R. Altman, S. Sathaye, and M. Gschwind. Optimizations and oracle parallelism with dynamic translation. In MICRO-32, Nov. 1999.
13. D. Burger and T.M. Austin. The SimpleScalar tool set, version 2.0. Computer Architecture News, pages 13–25, June 1997.
14. D. Stefanović and M. Martonosi. On availability of bit-narrow operations in generalpurpose applications. In 10th FPL, Villach, Austria, 2000.