Instruction scheduling for clustered VLIW architectures

Proceedings of the International Symposium on System Synthesis

Volumn 2000-January, Issue , 2000, Pages 41-46

  Sanchez J ^a   Gonzalez A ^a  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

Computer architecture; Continuous improvement; Delay effects; Electronic mail; Neck; Pipeline processing; Process design; Processor scheduling; Registers; VLIW

Indexed keywords

COMPUTER ARCHITECTURE; ELECTRONIC MAIL; PIPELINE PROCESSING SYSTEMS; PROCESS DESIGN; SCHEDULING; SYNTHESIS (CHEMICAL);

CONTINUOUS IMPROVEMENTS; DELAY EFFECTS; NECK; PIPELINE PROCESSING; PROCESSOR SCHEDULING; REGISTERS; VLIW;

VERY LONG INSTRUCTION WORD ARCHITECTURE;

EID: 34548789018     PISSN: 10801820     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSS.2000.874027     Document Type: Conference Paper

References (17)

1. E. Ayguadé, C. Barrado, A. González, J. Labarta, D. López, S. Moreno, D. Padua, F. Reig, Q. Riera and M. Valero, "Ictineo: a Tool for Research on ILP", in SC'96, Research Exhibit "Polaris at Work", 1996
2. A. Capitanio, D. Dytt and A. Nicolau, "Partitioned Register Files for VLIWs: A Preliminary Analysis of Tradeoffs", in Procs. of 25th. Int. Symp. on Microarchitecture, pp. 192-300, 1992
3. J. R. Ellis, "Bulldog: A Compiler for VLIW Architectures", MIT Press, pp. 180-184, 1986
4. M.M. Fernandes, J. Llosa and N. Topham, "Distributed Modulo Scheduling", in Procs. of Int. Symp. on High-Performance Computer Architecture, pp. 130-134, Jan. 1999
5. P. Glaskowsky, "MAP1000 unfolds at Equator", Microprocessor Report vol 12, no 16. Dec. 1998
6. S. Jang, S. Carr, P. Sweany and D. Kuras, "A Code Generation Framework for VLIW Architectures with Partitioned Register Banks", in Procs. of 3rd. Int. Conf. on Massively Parallel Computing Systems, April 1998
7. M. Lam, "Software pipelining: An Effective scheduling technique for VLIW Machines", in Procs. on Conf. on Programming Languages and Implementation Design, pp. 258-267, June 1993
8. D.M. Lavery and W.W. Hwu, "Unrolling-Based Optimizations for Modulo Scheduling", in Procs. of 28th. Int. Symp. on Microarchitecture, pp., 1995
9. J. Llosa, A. González, E. Ayguadé and M. Valero, "Swing Modulo Scheduling: A Lifetime-Sensitive Approach", in Procs. of Int. Conf. on Parallel Architectures and Compilation Techniques, pp. 80-86, Oct. 1996
10. E. Nystrom and A. E. Eichenberger, "Effective Cluster Assingment for Modulo Scheduling", in Procs. of 31th. Int. Symp. on Microarchitecture, pp.103-114, 1998
11. S. Palacharla, N.P. Jouppi, and J.E. Smith, "Complexity-Effective Superscalar Processors", in Procs. of the 24th. Int. Symp. on Computer Architecture, pp. 1-13, June 1997
12. E. Özer, S. Banerjia and T.M. Conte, "Unified Assign and Schedule: A New Approach to Scheduling for Clustered Register File Microarchitectures", in Procs. of 31st Int. Symp. on Microarchitecture, pp. 308-315, Nov. 1998
13. B.R. Rau and C.D. Glaeser, "Some Scheduling Techniques and an Easily Schedulable Horizontal Architecture for High Performance Scientific Computing", in Procs. on the 14th Ann. Workshop on Microprogramming, pp. 183-198, Oct. 1981
14. J. Sánchez and A. González, "Cache Sensitive Modulo Scheduling", in Procs. of 30th. Int. Symp. on Microarchitecture, pp. 338-348, Dec. 1997
15. Semiconductor Industry Association, "The National Technology Roadmap for Semiconductors: Technology Needs", 1997
16. Texas Instruments Inc., "TMS320C62x/67x CPU and Instruction Set Reference Guide", 1998
17. O. Wolfe and J. Bier, "TigerSharc Sinks Teeth Into VLIW", Microprocessor Report, vol. 12, no. 16, Dec. 1998.