Modulo scheduling with integrated register spilling for clustered VLIW architectures

Proceedings of the Annual International Symposium on Microarchitecture

Volumn , Issue , 2001, Pages 160-169

  Zalamea, Javier ^a   Llosa, Josep ^a   Ayguadé, Eduard ^a   Valero, Mateo ^a  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SOFTWARE; SCHEDULING; SHIFT REGISTERS;

INTEGRATED REGISTER SPILLING;

VERY LONG INSTRUCTION WORD ARCHITECTURE;

EID: 0035691538     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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