Scalable processors in the billion-transistor Era: IRAM

Computer

Volumn 30, Issue 9, 1997, Pages 75-78

  Kozyrakis, Christoforos E ^a,b   Perissakis, Stylianos ^a,c   Patterson, David ^a,d   Anderson, Thomas ^a,e,f,g   Asanović, Krste ^a,e,h   Cardwell, Neal ^a,i   Fromm, Richard ^a,j   Golbus, Jason ^a,k   Groibstad, Benjamin ^a,l   Keeton, Kimberly ^a,m   Thomas, Randi ^a   Treuhaft, Noah ^a,e,n   Yelick, Katherine ^a,o  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b UNIVERSITY OF CRETE   (Greece)

^c NATIONAL TECHNICAL UNIVERSITY OF ATHENS   (Greece)

^d UNIVERSITY OF CALIFORNIA   (United States)

^e UNIVERSITY OF CALIFORNIA   (United States)

^f HARVARD UNIVERSITY   (United States)

^g UNIVERSITY OF WASHINGTON   (United States)

^h UNIVERSITY OF CAMBRIDGE   (United Kingdom)

ⁱ The College of William and Mary   (United States)

^j Department of Obstetrics Gynecology   (United States)

^k DUKE UNIVERSITY   (United States)

^l UNIVERSITY OF MINNESOTA   (United States)

^m CARNEGIE MELLON UNIVERSITY   (United States)

ⁿ OBERLIN COLLEGE   (United States)

^o MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

more..

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; COST EFFECTIVENESS; MICROPROCESSOR CHIPS; STORAGE ALLOCATION (COMPUTER); TRANSISTORS;

BILLION TRANSISTORS; INTELLIGENT RANDOM ACCESS STORAGE (IRAM); VECTOR COMPILATION TECHNOLOGY;

RANDOM ACCESS STORAGE;

EID: 0031238171     PISSN: 00189162     EISSN: None     Source Type: Trade Journal    
DOI: 10.1109/2.612252     Document Type: Article

References (12)

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11. D.C. Burger, S. Kaxiras, and J.R. Goodman, "Data-Scalar Architectures," Proc. 24th Ann. Int'l Symp. Computer Architecture, ACM Press, May 1997, pp. 338-349.
12. S. Kaxiras, R. Sugumar, and J. Scharzmeier, "Distributed Vector Architecture: Beyond a Single-Vector IRAM," http://iram.cs.berkeley.edu/isca97-workshop/ (current July 23, 1997).