Evaluation of bus based interconnect mechanisms in clustered VLIW achitectures

Proceedings -Design, Automation and Test in Europe, DATE '05

Volumn II, Issue , 2005, Pages 730-735

  Gangwar, Anup ^a,b   Balakrishnan, M ^a   Panda, Preeti R ^a   Kumar, Anshul ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY DELHI   (India)

^b Calypto Design Systems   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; PIPELINE PROCESSING SYSTEMS; PROBLEM SOLVING; PROGRAM COMPILERS; SYSTEMS ANALYSIS;

DISTANT INSTRUCTIONS; MONOLITHIC REGISTER; RF-TO-RF TYPE; SCALABILITY PROBLEM;

INTERCONNECTION NETWORKS;

EID: 33646948783     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2005.141     Document Type: Conference Paper

References (21)

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