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Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 2001, Pages 175-184

A unified modulo scheduling and register allocation technique for clustered processors

(3) Codina, J M a Sanchez J a Gonzalez A a

a UNIVERSITAT POLITÈCNICA DE CATALUNYA (Spain)

Author keywords

Cluster assignment; Clustered architectures; Modulo scheduling; Register allocation; Spill code

Indexed keywords

COMPUTER ARCHITECTURE; HEURISTIC METHODS; SCHEDULING; STORAGE ALLOCATION (COMPUTER);

CLUSTERED ARCHITECTURES; REGISTER ALLOCATION TECHNIQUES;

MICROPROCESSOR CHIPS;

EID: 0035176849 PISSN: 1089795X EISSN: None Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper

Times cited : (51)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.