Low-power-design space exploration considering process variation using robust optimization

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 26, Issue 1, 2007, Pages 67-78

  Srivastava, Ashish ^a,b,c   Kachru, Tejasvi ^a,b,d   Sylvester, Dennis ^a,b  

^a IEEE   (United States)

^b UNIVERSITY OF MICHIGAN   (United States)

^c INTEL CORPORATION   (United States)

^d ADVANCED MICRO DEVICES   (United States)

Author keywords

Power minimization; Robust optimization; Variability; Yield allocation

Indexed keywords

POWER-MINIMIZATION TECHNIQUES; ROBUST OPTIMIZATION; STATISTICAL PARAMETERS; SUPPLY VOLTAGES; YIELD ALLOCATION;

CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; ELECTRIC POWER UTILIZATION; ENERGY DISSIPATION; OPTIMIZATION; ROBUSTNESS (CONTROL SYSTEMS); THRESHOLD VOLTAGE;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 33846261495     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2006.882491     Document Type: Article

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