A 100 nm node CMOS technology for practical SOC application requirement

Technical Digest-International Electron Devices Meeting

Volumn , Issue , 2001, Pages 511-514

  Ono, A ^a   Fukasaku, K ^a   Hirai, T ^a   Koyama, S ^a   Makabe, M ^a   Matsuda, T ^a   Takimoto, M ^a   Kunimune, Y ^a   Ikezawa, N ^a   Yamada, Y ^a   Koba, F ^a   Imai, K ^a   Nakamura, N ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; CMOS INTEGRATED CIRCUITS; DIELECTRIC FILMS; GATES (TRANSISTOR); LEAKAGE CURRENTS; MOSFET DEVICES; NITRIDES; OPTIMIZATION; OXIDES; REDUCTION; SURFACES; TEMPERATURE;

CMOS TECHNOLOGY; GATE DIELECTRIC; OXYNITRIDE; SYSTEM ON CHIP APPLICATION;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0035714566     PISSN: 01631918     EISSN: None     Source Type: Journal    
DOI: 10.1109/IEDM.2001.979557     Document Type: Article

References (3)