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Volumn 2005, Issue , 2005, Pages 829-836

Statistical timing analysis with two-sided constraints

Author keywords

[No Author keywords available]

Indexed keywords

MATHEMATICAL MODELS; STATISTICAL METHODS; SYSTEMS ANALYSIS;

EID: 33751415873     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2005.1560178     Document Type: Conference Paper
Times cited : (23)

References (15)
  • 1
    • 0031342511 scopus 로고    scopus 로고
    • The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits
    • December
    • M. Eisele, J. Berthold, D. Schmitt-Landsiedel, and R. Mahnkopf. The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits. IEEE Trans. on VLSI, 5(4):360-368, December 1997.
    • (1997) IEEE Trans. on VLSI , vol.5 , Issue.4 , pp. 360-368
    • Eisele, M.1    Berthold, J.2    Schmitt-Landsiedel, D.3    Mahnkopf, R.4
  • 3
    • 0033350553 scopus 로고    scopus 로고
    • Statistical device models for worst case flies and electrical test data
    • November
    • K. Singhal and V. Visvanathan. Statistical device models for worst case flies and electrical test data. IEEE Trans. on Semiconductor Manufacturing, 12(4): 470-484, November 1999.
    • (1999) IEEE Trans. on Semiconductor Manufacturing , vol.12 , Issue.4 , pp. 470-484
    • Singhal, K.1    Visvanathan, V.2
  • 4
    • 0042635808 scopus 로고    scopus 로고
    • Death, taxes and failing chips
    • Anaheim, CA, June 2-6
    • C. Visweswariah. Death, taxes and failing chips. In Design Automation Conf., pages 343-347, Anaheim, CA, June 2-6 2003.
    • (2003) Design Automation Conf. , pp. 343-347
    • Visweswariah, C.1
  • 5
    • 0041633575 scopus 로고    scopus 로고
    • Statistical timing for parametric yield prediction of digital integrated circuits
    • Anaheim, CA, June 2-6
    • J. A. G. Jess, K. Kalafala, W. R. Naidu, R. H. J. M. Otten, and C. Visweswariah. Statistical timing for parametric yield prediction of digital integrated circuits. In Design Automation Conf., pages 932-937, Anaheim, CA, June 2-6 2003.
    • (2003) Design Automation Conf. , pp. 932-937
    • Jess, J.A.G.1    Kalafala, K.2    Naidu, W.R.3    Otten, R.H.J.M.4    Visweswariah, C.5
  • 6
    • 0041633857 scopus 로고    scopus 로고
    • Computation and refinement of statistical bounds on circuit delay
    • Anaheim, CA, June 2-6
    • A. Agarwal, D. Blaauw, V. Zolotov, and S. Vrudhula. Computation and refinement of statistical bounds on circuit delay. In Design Automation Conf., pages 348-353, Anaheim, CA, June 2-6 2003.
    • (2003) Design Automation Conf. , pp. 348-353
    • Agarwal, A.1    Blaauw, D.2    Zolotov, V.3    Vrudhula, S.4
  • 7
    • 0348040110 scopus 로고    scopus 로고
    • Block-based static timing analysis with uncertainty
    • San Jose, CA, November 9-13
    • A. Devgan and C. Kashyap. Block-based static timing analysis with uncertainty. In IEEE/ACM In'l Conf. on Computer-Aided Design, pages 607-614, San Jose, CA, November 9-13 2003.
    • (2003) IEEE/ACM In'l Conf. on Computer-aided Design , pp. 607-614
    • Devgan, A.1    Kashyap, C.2
  • 9
    • 0346778721 scopus 로고    scopus 로고
    • Statistical timing analysis considering spatial correlations using a single PERT-like traversal
    • San Jose, CA, November 9-13
    • H. Chang and S. S. Sapatnekar. Statistical timing analysis considering spatial correlations using a single PERT-like traversal. In IEEE/ACM Int'l Con/, on Computer-Aided Design, pages 621-625, San Jose, CA, November 9-13 2003.
    • (2003) IEEE/ACM Int'l Con/, on Computer-aided Design , pp. 621-625
    • Chang, H.1    Sapatnekar, S.S.2
  • 10
    • 0348040085 scopus 로고    scopus 로고
    • Statistical timing analysis for intra-die process variations with spatial correlations
    • San Jose, CA, November 9-13
    • A. Agarwal, D. Blaauw, and V. Zolotov. Statistical timing analysis for intra-die process variations with spatial correlations. In IEEE/ACM Int'l Conference on Computer-Aided Design, pages 900-907, San Jose, CA, November 9-13 2003.
    • (2003) IEEE/ACM Int'l Conference on Computer-aided Design , pp. 900-907
    • Agarwal, A.1    Blaauw, D.2    Zolotov, V.3
  • 11
    • 4444247313 scopus 로고    scopus 로고
    • Statistical timing analysis based on a timing yield model
    • San Diego, CA, June 7-11
    • F. Najm and N. Menezes. Statistical timing analysis based on a timing yield model. In Design Automation Conference, pages 460-465, San Diego, CA, June 7-11 2004.
    • (2004) Design Automation Conference , pp. 460-465
    • Najm, F.1    Menezes, N.2
  • 12
    • 0034823025 scopus 로고    scopus 로고
    • Impact of within-die parameter fluctuations on future maximum clock frequency distributions
    • K. A. Bowman and J. D. Meindl. Impact of within-die parameter fluctuations on future maximum clock frequency distributions. In IEEE Custom Integrated Circuits Conf., pages 229-232, 2001.
    • (2001) IEEE Custom Integrated Circuits Conf. , pp. 229-232
    • Bowman, K.A.1    Meindl, J.D.2
  • 13
    • 0001796208 scopus 로고    scopus 로고
    • Statistical circuit modeling and optimization
    • June
    • S. G. Duvall. Statistical circuit modeling and optimization. In Int'l Workshop on Statistical Metrology, pages 56-63, June 2000.
    • (2000) Int'l Workshop on Statistical Metrology , pp. 56-63
    • Duvall, S.G.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.