Simultaneous subthreshold and gate-oxide tunneling leakage current analysis in nanometer CMOS design

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2003-January, Issue , 2003, Pages 287-292

  Lee, Dongwoo ^a   Kwong, Wesley ^a   Blaauw, David ^a   Sylvester, Dennis ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Circuits; Curve fitting; Gate leakage; Leakage current; Minimization; Nonlinear equations; Predictive models; Semiconductor device modeling; Tunneling; Voltage

Indexed keywords

CURVE FITTING; ELECTRIC POTENTIAL; ELECTRON TUNNELING; INTEGRATED CIRCUIT DESIGN; NETWORKS (CIRCUITS); NONLINEAR EQUATIONS; OPTIMIZATION; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICES; SPICE;

BENCHMARK CIRCUIT; GATE LEAKAGES; LARGE CIRCUITS; PREDICTIVE MODELS; SPICE SIMULATIONS; STATE-DEPENDENT; SUB-THRESHOLD LEAKAGE; TUNNELING LEAKAGE CURRENT;

LEAKAGE CURRENTS;

EID: 0042196141     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2003.1194747     Document Type: Conference Paper

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