A 1 Tb/s 3 W inductive-coupling transceiver for 3D-stacked inter-chip clock and data link

IEEE Journal of Solid-State Circuits

Volumn 42, Issue 1, 2007, Pages 111-121

  Miura, Noriyuki ^b   Mizoguchi, Daisuke ^b   Inoue, Mari ^b   Niitsu, Kiichi ^b   Nakagawa, Yoshihiro ^c   Tago, Masamoto ^c   Fukaishi, Muneo ^a,c   Sakurai, Takayasu ^a,d   Kuroda, Tadahiro ^a,b  

^a IEEE

^b KEIO UNIVERSITY   (Japan)

^c NEC CORPORATION   (Japan)

^d UNIVERSITY OF TOKYO   (Japan)

Author keywords

Inductor; SiP; Three dimensional; Wireless inter connect

Indexed keywords

BI-PHASE MODULATION (BPM); DATA LINK; NOISE IMMUNITY; WIRELESS INTERCONNECTS;

CMOS INTEGRATED CIRCUITS; ELECTRIC INDUCTORS; FREQUENCY MODULATION; MICROPROCESSOR CHIPS; TELECOMMUNICATION LINKS; THREE DIMENSIONAL; TIME DIVISION MULTIPLE ACCESS;

TRANSCEIVERS;

EID: 33846204282     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.886554     Document Type: Article

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