A 28.5GB/s CMOS non-blocking router for terabits/s connectivity between multiple processors and peripheral I/O nodes

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2001, Pages

  Nair, R ^a   Borkar, N Y ^a   Browning, C S ^a   Dermer, G E ^a   Erraguntla, V ^a   Govindarajulu, V ^a   Pangal, A ^a   Prijic, J D ^a   Rankin, L ^a   Seligman, E ^a   Vangal, S ^a   Wilson, H A ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CMOS INTEGRATED CIRCUITS; CROSSBAR EQUIPMENT; DATA TRANSFER; DIGITAL COMMUNICATION SYSTEMS; ERROR ANALYSIS; INTERFACES (COMPUTER); OPTICAL LINKS; PACKET NETWORKS; PHASE LOCKED LOOPS;

NON-BLOCKING ROUTERS;

ROUTERS;

EID: 0035061182     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. A 900 Mb/s bidirectional signaling scheme
2. Cavallino: The teraflops router and NIC
3. A 2.5 Gb/s bidirectional signaling technology
4. When are transmission-line effects important for on-chip interconnections?
5. 3.2GHz, 6.4Gb/s per wire signaling in 0.18μm CMOS