A 160Gb/s interface design configuration for multichip LSI

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 47, Issue , 2004, Pages

  Ezaki, Takayuki ^a   Kondo, Kazuhiro ^a   Ozaki, Hiroshi ^a   Sasaki, Naoto ^a   Yonemura, Hitoshi ^a   Kitano, Masaaki ^a   Tanaka, Shuji ^a   Hirayama, Teruo ^a  

^a SONY CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

HIGH POWER CONSUMPTION; MEMORY CHIPS;

DATA STORAGE EQUIPMENT; DYNAMIC RANDOM ACCESS STORAGE; ELECTRIC POWER UTILIZATION; FABRICATION; FLIP FLOP CIRCUITS; LSI CIRCUITS; PERFORMANCE;

MICROPROCESSOR CHIPS;

EID: 2442686519     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. T. Hirayama et al., "Impact of Embedded DRAM Logic Devices on the Semiconductor Manufacturing," Proceedings of SPIE, vol. 4409, pp. 12-22, 2001.
2. D. Buss, Texas Instrument et al., "SOC versus SIP," 2002 Symposium On VLSI Technology Digest of Technical Papers, pp. 142.