A 195-gb/s 1.2-W inductive inter-chip wireless superconnect with transmit power control scheme for 3-D-stacked system in a package

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 1, 2006, Pages 23-34

  Miura, N ^a   Mizoguchi, D ^a   Inoue, M ^a   Sakurai, T ^a   Kuroda, T ^a  

^a KEIO UNIVERSITY   (Japan)

Author keywords

1. 2 W; 195 Gbit s; 3D stacked system in a package; 50 micron; CMOS technology; Crosstalk; Inductive coupling; Inductive interchip wireless superconnect; Low power single end transmitter; Power dissipation; Transmit power control scheme; Wireless interconnect

Indexed keywords

CMOS INTEGRATED CIRCUITS; COUPLED CIRCUITS; CROSSTALK; INTEGRATED CIRCUITS; TRANSCEIVERS;

1. 2 W; 195 GBIT/S; 3D STACKED SYSTEM IN A PACKAGE; CMOS TECHNOLOGY; INDUCTIVE COUPLING; INDUCTIVE INTERCHIP WIRELESS SUPERCONNECT; LOW POWER SINGLE END TRANSMITTER; POWER DISSIPATION; TRANSMIT POWER CONTROL SCHEME; WIRELESS INTERCONNECT;

WIRELESS TELECOMMUNICATION SYSTEMS;

EID: 31344436459     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2005.858625     Document Type: Article

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