A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2006, Pages

  Miura, Noriyuki ^a   Mizoguchi, Daisuke ^a   Inoue, Mari ^a   Niitsu, Kiichi ^a   Nakagawa, Yoshihiro ^b   Tago, Masamoto ^b   Fukaishi, Muneo ^b   Sakurai, Takayasu ^c   Kuroda, Tadahiro ^a  

^a KEIO UNIVERSITY   (Japan)

^b NEC CORPORATION   (Japan)

^c UNIVERSITY OF TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; CMOS INTEGRATED CIRCUITS; CROSSTALK; PHASE MODULATION; TIME DIVISION MULTIPLE ACCESS;

INDUCTIVE COUPLING TRANSCEIVERS; NOISE IMMUNITY;

TRANSCEIVERS;

EID: 33846207670     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)

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