A 100 Gb/s transceiver with GND-VDD common-mode receiver and flexible multi-channel aligner

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2002, Pages 264-265+465+263

  Tanaka, Kenichi ^a   Fukaishi, Muneo ^a   Takeuchi, Masahiro ^a   Yoshida, Nobuhide ^a   Minami, Kouichirou ^a   Yamaguchi, Kouichi ^a   Uchida, Hiroyuki ^a   Morishita, Yasuyuki ^a   Sakamoto, Takehiko ^a   Kaneko, Tomoyuki ^a   Soda, Masaaki ^a   Kurisu, Masakazu ^a   Saeki, Takanori ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ATTENUATION; BANDWIDTH; BIT ERROR RATE; CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; PHASE LOCKED LOOPS; POWER AMPLIFIERS; VARIABLE FREQUENCY OSCILLATORS; WAVEFORM ANALYSIS;

CLOCK AND DATA RECOVERY (CDR); COMMON MODE RECEIVERS;

TRANSCEIVERS;

EID: 0036110464     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. A 2 Gb/s 21 CH low-latency transceiver circuit for inter-processor communication
2. 2.5 GHz 4-phase clock generator with scalable and no feedback loop architecture
3. An 84-mW 4-Gb/s clock and data recovery circuit for serial link applications