A 1.2Gb/s/pin wireless superconnect based on Inductive Inter-chip Signaling (IIS)

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 47, Issue , 2004, Pages

  Mizoguchi, Daisuke ^a   Yusof, Yusmeeraz Binti ^a   Miura, Noriyuki ^a   Sakurai, Takayasu ^b   Kuroda, Tadahiro ^a  

^a KEIO UNIVERSITY   (Japan)

^b UNIVERSITY OF TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

PROCESS COMPLEXITY; WIRELESS INTERFACES;

BANDWIDTH; CMOS INTEGRATED CIRCUITS; FLIP FLOP CIRCUITS; INTERCONNECTION NETWORKS; SIGNALING; TRANSCEIVERS; WIRELESS TELECOMMUNICATION SYSTEMS;

MICROPROCESSOR CHIPS;

EID: 2442653859     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. J. Burns et al., "Three-Dimensional Integrated Circuits for Low-Power, High-Bandwidth Systems on a Chip," ISSCC Dig. Tech. Papers, pp. 268-269, Feb. 2001.
2. S. Mick et al., "4Gbps High-Density AC Coupled Interconnection, " 2002 CICC, pp. 133-140.
3. K. Kanda et al., "1.27Gb/s/pin 3mW/pin Wireless Superconnect (WSC) Interface Scheme," ISSCC Dig. Tech. Papers, pp. 186-187, Feb. 2003.
4. M. Usami et al., "Powder LSI: An Ultra Small RF Identification Chip for Individual Recognition Applications," ISSCC Dig, Tech. Papers, pp. 398-399, Feb. 2003.