A scalable 160Gb/s switch fabric processor with 320Gb/s memory bandwidth

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 47, Issue , 2004, Pages

  Paul, Gideon ^a   Khan, Aurangzeb ^b   Zeiger, Micha ^a   Cohn, Alex ^a   Dramon, David ^a   Le, Duc ^b   Naviasky, Eric ^b   Grigoriants, Evgeny ^a   Malkin, Galina ^a   Malobani, Itzik ^a   Yanuka, Izik ^a   Yu, John ^b   Kung, Joseph ^b   Gnor, Liora ^a   Shiterit, Maor ^a   Rozen, Rami ^a   Gabe, Raz ^a   Hadas, Shahar ^a   Kelly, Thomas ^b   Wilson, Thomas ^b   Nguyen, Trung ^b   Evans, William ^b   Hayon, Yoel ^a   more..

^a TeraChip   (Israel)

^b CADENCE DESIGN SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MEMORY BANDWIDTH; POWER DISSIPATION; SCALABLE SYSTEMS; SWITCH FABRICS (SF);

COMPUTER SIMULATION; CROSSTALK; FLIP CHIP DEVICES; INTEGRATED CIRCUITS; MULTIPLEXING; OPTICAL INTERCONNECTS; QUEUEING NETWORKS; RANDOM PROCESSES; SWITCHES; SYNCHRONIZATION; TOPOLOGY;

BANDWIDTH;

EID: 2442669246     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. N. McKeown, "An Introduction to Packet Switching," EE 370, Stanford University, Jan. 2000
2. G. None, M. Hamadi, "On the Provision of Quality-of-Service Guarantees for Input Queued Switches," IEEE Communication Magazine, vol. 38, pp 62-69, Dec. 2000