A 2Gb/s 21CH low-latency transceiver circuit for inter-processor communication

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2001, Pages 60-61+430

  Tanahashi, T ^a   Kurisu, M ^a   Yamaguchi, H ^a   Nedachi, T ^a   Arai, M ^a   Tomari, S ^a   Matsuzaki, T ^a   Nakamura, K ^a   Fukaishi, M ^a   Naramoto, S ^a   Sato, T ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COUNTING CIRCUITS; ELECTRIC CLOCKS; ELECTRIC DELAY LINES; PROGRAM PROCESSORS; SERVERS; SUPERCOMPUTERS;

PUSH-PULL DRIVERS;

TRANSCEIVERS;

EID: 0035054795     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. A 2B parallel 1.25Gb/s interconnect I/O interface with self-configurable link and plesiochronous clocking
2. A portable Digital DLL Architecture for CMOS Interface Circuits