A 20Gb/s CMOS multi-channel transmitter and receiver chip set for ultra-high resolution digital display

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2000, Pages 260-261

  Fukaishi, M ^a   Nakamura, K ^a   Heiuchi, H ^a   Hirota, Y ^a   Nakazawa, Y ^a   Ikeno, H ^a   Hayama, H ^a   Yotsuyanagi, M ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DATA COMMUNICATION SYSTEMS; DISPLAY DEVICES; MICROPROCESSOR CHIPS;

DIGITAL DISPLAY; MULTI-CHANNEL TRANSMITTERS;

TRANSCEIVERS;

EID: 0034429641     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. A 4.25Gb/s CMOS fiber channel transceiver with asynchronous tree-type demultiplexer and frequency conversion architecture
2. A semidigital dual delay-locked loop
3. Clock/data recovery PLL using half-frequency clock
4. A DC-balanced partitioned-block, 8B/10B transmission code