BIST for network-on-chip interconnect infrastructures

Proceedings of the IEEE VLSI Test Symposium

Volumn 2006, Issue , 2006, Pages 30-35

  Grecu, Cristian ^a   Pande, Partha ^b   Ivanov, André ^a   Saleh, Res ^a  

^a UNIVERSITY OF BRITISH COLUMBIA   (Canada)

^b Washington State University   (United States)

Author keywords

Built in self test; Interconnect infrastructure; Multicast test; Network on chip; Unicast test

Indexed keywords

BUILT-IN SELF TEST; CROSSTALK; DATA TRANSFER; MICROPROCESSOR CHIPS;

INTERCONNECT INFRASTRUCTURE; MULTICAST TEST; NETWORK-ON-CHIP; UNICAST TEST;

OPTICAL INTERCONNECTS;

EID: 33751090124     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2006.22     Document Type: Conference Paper

References (24)

1. L. Benini, G. De Micheli, "Networks on Chips: A New SoC Paradigm" Computer, Volume: 35 Issue: 1, Jan. 2002, pp.: 70-78.
2. P. Magarshack, P.G. Paulin, "System-on-Chip beyond the Nanometer Wall", Proceedings of DAC, June 2-6, 2003, Anaheim, USA, pp. 419-424.
3. S. Kumar et al, "A Network on Chip Architecture and Design Methodology," Proceedings of ISVLSI, Pittsburgh, USA, 2002, pp. 117-124.
4. W. J. Dally, B. Towles, "Route Packets, Not Wires: On-Chip Interconnection Networks", Proceedings of DAC, Las Vegas, Nevada, USA, June 18-22, 2001, pp. 683-689.
5. P. Guerrier, A. Greiner,"A Generic Architecture for on-chip Packet-switched Interconnections", Proceedings of DATE, Paris, France, March 27-30, 2000, pp. 250-256.
6. P. P. Pande, C. Grecu, A. Ivanov, R. Saleh, "Design of a Switch for Network on Chip Applications", Proceedings of ISCAS, Bangkok, May 2003, Volume 5, pp. 217-220.
7. C. Grecu, P. P. Pande, A. Ivanov, R Saleh "Structured Interconnect Architecture: A Solution for the Non-Scalability of Bus-Based SoCs", Great Lakes Symposium on VLSI, Boston, USA 26-28 April 2004, pp 192-195.
8. L. Benini, D. Bertozzi, "Xpipes: A Network-on-chip Architecture for Gigascale Systems-on-chip", IEEE Circuits and Systems Magazine, Volume 4, Issue 2, 2004, pp. 18-31.
9. E. Cota, Luigi Caro, Flavio Wagner, Marcelo Lubaszewski, "Power aware NoC Reuse on the Testing of Core-Based Systems", Proceedings of ITC 2003, pp. 612-621.
10. P. Pande, C. Grecu, A. Ivanov, R. Saleh, G. De Micheli, "Design, Synthesis and Test of Networks on Chip", IEEE Design and Test of Computers, Vol. 22, No. 5, 2005, pp. 404-413.
11. C. Grecu, P. Pande, B. Wang, A. Ivanov, R. Saleh, "Methodologies and Algorithms for Testing Switch-Based NoC Interconnects", Proceedings of IEEE DFT 2005.
12. E. J. Marinissen, R. Arendsen, G. Bos, H. Dingemanse, M. Lousberg, C. Wouters, "A Structured and Scalable Mechanism for Test Access to Embedded Reusable Cores", Proceedings of ITC 1998, pp. 284-293.
13. B. Vermeulen, J. Dielissen, K. Goossens, C. Ciordas, "Bringing Communications Networks on a Chip: Test and Verification Implications", IEEE Communications Magazine, Volume 41, Issue 9, sept. 2003, pp. 74-81.
14. M. Nahvi, A. Ivanov, "Indirect Test Architecture for SoC Testing", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 23, Issue 7, July 2004, pp. 1128-1142.
15. M. Cuviello, S. Dey, X. Bai, Y. Zhao, "Fault Modeling and Simulation for Crosstalk in System-on-Chip Interconnects", Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, Nov. 1999, pp. 297-303
16. X. Bai, S. Dey, "High-level Crosstalk Defect Simulation for System-on-Chip Interconnects", Proceedings of the 19th IEEE VLSI Test Symposium, Marina del Rey, CA, April 2001, pp. 169-175
17. S. Sridhara, N. Shanbhag, "Coding for Reliable On-Chip Busses: Fundamental Limits and Practical Codes", Proceedings of the IEEE Conference on VLSI Design 2005, pp. 417-422
18. D. Rossi, A. K. Nieuwland, A. Katoch, C. Metra, "Exploiting ECC Redundancy to Minimize Crosstalk Impact", IEEE Design and Test of Computers, Jan/Feb 2005, Vol. 22, No. 1, pp. 59-70.
19. P. P. Pande, C. Grecu, A. Ivanov, R. Saleh, "Switch-Based Interconnect Architecture for Future Systems on Chip", Proceedings of SPIE, VLSI Circuits and Systems, Vol. 5117, pp. 228-237, 2003, Maspalomas, Spain.
20. th ACM Annual International Symposium on Computer Architecture (ISCA-24), June 1997.
21. P. Kapur, G. Chandra, J. McVittie, K. C. Saraswat, "Technology and Reliability Constrained Future Copper Interconnects - Part II: Performance Implications", IEEE Transactions on Electron Devices, Vol. 49, No. 4, April 2002 pp. 598-604.
22. J. Duato, S. Yalamanchili, L. Ni, Interconnection Networks - An Engineering Approach, Morgan Kaufmann, 2002.
23. C. Grecu, P. Pande, A. Ivanov, R. Saleh, "Timing Analysis of Network on Chip Architectures for MP-SoC Platforms", Microelectronics Journal, Elsevier, Vol. 36(9), pp. 833-845.
24. Pasquale Cocchini, "Concurrent Flip-Flop and Repeater Insertion for High Performance Integrated Circuits", Proceedings of ICCAD 2002, pp. 268-273.