High-level crosstalk defect simulation for system-on-chip interconnects

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2001, Pages 169-175

  Bai, X ^a   Dey, S ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Crosstalk; Defect simulation; High level; Interconnect test; System on chip

Indexed keywords

COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION; CROSSTALK; DEFECTS; ERROR ANALYSIS; FAILURE ANALYSIS; INTERCONNECTION NETWORKS; MATHEMATICAL MODELS; RELIABILITY;

CROSSTALK DEFECT; DEEP SUBMICRON TECHNOLOGY; INTERCONNECT TEST; SYSTEM-ON-CHIPS;

INTEGRATED CIRCUIT TESTING;

EID: 0035005177     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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